# Carry select adder - Time calculation

• MHB
• mathmari
This can be done by multiplying the number of sub-sections adders by the delay time of an elementary gate and adding the delay time of all multiplexers. In summary, the binary pick-up adder has two halves and the addition is done simultaneously. The calculation time of the retained output can be found by multiplying the number of sub-sections adders by the delay time of an elementary gate and adding the delay time of all multiplexers.
mathmari
Gold Member
MHB
Hey! :giggle:

a) Suppose a binary pick-up adder (carry-select) of $32$-bits, comprising $4$ sub-sections adders spreading carry of range $8$ bits. Show the values obtained internally in the circuit of this adder to perform the addition of the numbers $01011001101100111110110011001101$ and $10010110011111000001101100110110$. Specifically, show the input and output values on each $1$-bit full adder circuit, as well as the input and output values on all multiplexers in the circuit. If each complete $1$-bit adder circuit and each multiplexer circuit cause a delay of $2T$ in the execution of the operation, where $T$ is the delay time of an elementary gate, find the calculation time of the retained output.

b) Repeat the above if the $32$-bit adder includes $6$ sub-sections adders spreading carry, ranging in order from less to more important sections $2$, $4$, $4$, $6$, $6$, and $10$ bits.
The idea of that method is :

The adder is divided into two halves of equal length. And for both halves, the addition is started at the same time. In the left (more significant) half we don't know whether the carry input of the rightmost full adder is a $1$ or a $0$. Therefore, we do the addition of the left half twice at the same time, once with a $0$ at the carry input and once with a $1$. If the right half with its addition is done, we know the incoming carry of the left half. So we know which of the results is the right one, which we then select (select). The other (wrong) result is simply discarded.

Is that correct?

So we split $01011001101100111110110011001101$ into $a_1=0101100110110011$ and $a_2=1110110011001101$, right?

And we split also $10010110011111000001101100110110$ into $b_1=1001011001111100$ and $b_2=0001101100110110$, right?

Then we add $a_1+b_1$ wih carry $0$ and $a_1+b_1$ wih carry $1$.

We also calculate the addition $a_2+b_2$.

As for the addition $a_1+b_1$ wih carry $0$ : $$0101100110110011+1001011001111100=1111000000101111$$

As for the addition $a_1+b_1$ wih carry $1$ : $$0101100110110011+1001011001111100=1111000000110000$$

As for the addition $a_2+b_2$ :
$$1110110011001101+0001101100110110=0000100000000011\ \ \text{ with carry } 1$$ So we select the second case of $a_1+b_1$.Is everything correct? How could we continue? :unsure:

Yes, everything is correct. To continue, you need to calculate the values obtained internally in the circuit of the adder for each $1$-bit full adder circuit and each multiplexer circuit. Then, you can use the information to find the calculation time of the retained output.

## 1. How does a carry select adder work?

A carry select adder is a type of digital circuit used to add two binary numbers. It works by breaking down the addition process into smaller, parallel computations, and then combining the results to obtain the final sum.

## 2. How is the time delay of a carry select adder calculated?

The time delay of a carry select adder is calculated by adding the propagation delays of its individual components, such as AND, OR, and XOR gates. The carry select adder's time delay is also affected by the number of bits being added and the frequency of the clock signal.

## 3. What is the significance of time calculation in a carry select adder?

Time calculation is important in a carry select adder because it determines the speed at which the addition operation can be performed. The shorter the time delay, the faster the adder can process binary numbers and produce an accurate result.

## 4. How does the carry select adder's time delay compare to other types of adders?

The carry select adder typically has a longer time delay compared to other types of adders, such as the carry ripple adder or the carry look-ahead adder. This is because it requires additional logic and gates to perform the parallel computations and combine the results.

## 5. Can the time delay of a carry select adder be reduced?

Yes, the time delay of a carry select adder can be reduced by using faster components, optimizing the design, or implementing parallel processing techniques. However, this may come at the cost of increased complexity and higher production costs.

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