1. PF Contest - Win "Conquering the Physics GRE" book! Click Here to Enter
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

CE amp midband gain and PSPICE

  1. Feb 26, 2013 #1
    I’m in the process of writing a lab report after testing a cascaded common-emitter amp. The second transistor input is the collector output (collector to base) which I understand to be an emitter follower?

    I have used PSPICE to measure the gain when a 20mV signal is applied and I have measured the resulting output peak-to-peak voltage to be a maximum of 2.2V which gives a gain of 40.8dB.

    I have plotted the frequency response (20log(output/input)) using PSPICE and I’m getting a midband gain of around 43dB, which would mean an output of around 2.8V which is well over what I have read from the output signal plot.

    The bottom of the output signal seems to be clipped and I was wondering if this could have anything to do with the results not matching up?
  2. jcsd
  3. Feb 26, 2013 #2

    rude man

    User Avatar
    Homework Helper
    Gold Member

    Anytime you have a clipped signal you can throw out all the data.

    It would help if you described your complete circuit including input voltage.
  4. Feb 26, 2013 #3
    I've attached the circuit diagram, Cc2 can be omitted the main point of this assignment was to see the effects of changing the value of capacitor Cc.

    Input signal is 20mV (19.71mV measured PSPICE voltage)
    Output Signal clipped at bottom = 2.09V measured with PSPICE.

    Gain also measured = 43.37 dB

    Vcc = +15V

    Attached Files:

    Last edited: Feb 26, 2013
  5. Feb 26, 2013 #4


    User Avatar

    Staff: Mentor

    Wow, that's a giant Ce!
  6. Feb 26, 2013 #5

    rude man

    User Avatar
    Homework Helper
    Gold Member

    This is a far from trivial circuit to analyze.

    You did not mention any frequencies, especially the one where you get the clipping. Need that.

    Next: the 1st stage is a Miller integrator. So right away you have dynamics (frequency-sensitivities) to contend with. This is an ac, not a dc, equation.

    (Assuming an infinite-beta transistor and an ac-grounded emitter, one of your equations will be dVc/dt + V1/RB= 0 where V1 is the voltage at the junction of CIN/R1/R2/R8.)

    Yes, the second stage is an emitter follower.

    I suggest removing CC, CC2 and CL from the simulation at first. See how the circuit behaves at the various nodes. You can then add small amounts of CC at a time to see the effects of the Miller integrator effect on Q1n and small amounts of CL.
  7. Feb 27, 2013 #6
    I’ve changed the value of Cc and at 470pF the bandwidth is 15kHz then doubling the Cc the bandwidth almost halves to 8kHz.

    Clipping starts at around 80Hz
  8. Feb 27, 2013 #7

    rude man

    User Avatar
    Homework Helper
    Gold Member

    Tell you what, this circuit is more or less a disaster. The ac gain at frequencies above about 2.7 KHz (the cutoff frequency of the input stage) is directly proportional to the beta of Q1 which is very poor design. Where did this design come from? I would not pursue this design any further without significant changes ...
  9. Feb 27, 2013 #8
    I’m doing an assignment which is to analyse the CE amp that incorporates Q1. This involves DC analysis and bandwidth/3db frequencies when the value of Cc is changed.
    Raising the value seems to shorten the bandwidth which I’m sure you already know. I still have to investigate the reason for this.

    The adding of Q2 to the amp is optional and I was hoping that there was a simple answer why the gain doesn’t match the output/input.

    I have gathered from what you have said that if the signal is clipped the output is not going to be as expected. Is this due to the lack of linearity?
  10. Feb 27, 2013 #9

    rude man

    User Avatar
    Homework Helper
    Gold Member

    Yes, clipping implies nonlinearity. Not only is the intended signal reduced but clipping implies harmonic generation.

    This circuit is too difficult to analyze. If you want a more or less stably biased and predictable CE circuit for Q1, let me know. I really can't work with this circuit.

    (I can give you one with your input R-C network Cin + Rb, plus just 3 resistors and Q1. Your Rc would be the same 5.1K. Gain = 40 dB. You could also add CC if you wanted.
    Do you have a -15V supply available?)
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted

Similar Threads - midband gain PSPICE Date
Finding the magnitude of the voltage gain in dB Wednesday at 11:27 AM
Expression for closed loop gain of differential amplifier Dec 21, 2017
Finding Voltage Gain Dec 9, 2017
Midband region Aug 18, 2008