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Chip layout

  1. Dec 10, 2006 #1
    Does anyone know why I/O pads are necessary in IC layout?
    is it because there are input/output signals coming in/out of the chip and one would want to interface it to something else?
    Is it really that simple? or I am missing something....
     
    Last edited: Dec 10, 2006
  2. jcsd
  3. Dec 10, 2006 #2

    chroot

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    The biggest reason is that the external world is connected to the IC by bond wires. The bond wires, while still thinner than human hairs, are absolutely enormous when compared to IC feature sizes. Futhermore, the bonding machine is not perfect, and doesn't always land its bonding wires in exactly the right spot.

    Besides, you need some kind of metallic (ohmic) connection between the chip and the outside world; you can't easily bond a wire to silicon.

    The solution is to use a little metal pad, large enough that the bonder can hit it nearly 100% of the time.

    - Warren
     
  4. Dec 10, 2006 #3
    ooooooohhh..... ok.... now i get it... thanks :)
     
  5. Dec 10, 2006 #4

    chroot

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    By the way, you didn't specify whether you're talking about analog or digital pads, but there's a bit of a nomeclature problem in the industry.

    An 'analog pad' is essentially just a metallic (ohmic) contact, also called simply a 'bond pad.' The term 'digital pad,' however, is sometimes used to refer to both the bond pad AND the digital pad driver and amplifier used for I/O.

    If you're asking "why do ICs need special pad drivers?" then the answer is because off-chip lines have large capacitance, and you need a very large driver, capable of large currents, to quickly charge and discharge that capacitance.

    - Warren
     
  6. Dec 10, 2006 #5
    I think I meant 'analog'... and actually did not know about the digital part of it. So, they actually use amplifiers for I/O? thanks for the extra stuff...
     
  7. Dec 11, 2006 #6
    ok, one more thing... I recently did a layout of my chip in SOC encounter and I had to pad it with no-connect pins, i.e. dummy pins. Since the design was presupposing a square chip with 40 pins, 10-N, 10-S, 10-E, 10-W, I padded everything up to 40, I had only 19 I/O proper. However I noticed the pins were spaced out. I ran verify connectivity and did not get any violations. But then when I added more no-connect pins to fill in the spacing around the core I got 600-some connectivity violations. How do I fix this?
     
    Last edited: Dec 11, 2006
  8. Dec 11, 2006 #7

    chroot

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    I hope you ran place & route again after you laid down your dummy pads?

    - Warren
     
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