1. The problem statement, all variables and given/known data if [itex]V_g = 54V[/itex] find [itex]i_0, i_1, i_2[/itex] 3. The attempt at a solution In the left most closed loop, Since the source voltage is 54, I assumed there must be a voltage drop across the 12Ω and 6Ω resistors equal to 54. This makes VΔ 18V. Next I tried to KCL the node below it, but it immediately confused me. If the current around the closed loop is 3A (which is what I calculated by doing a KVL of that leftmost loop), then how can there be any more current flowing into that node? Shouldn't i0 be 0? Then, even if it is, that means in the righthand part of the circuit, one node has three currents leaving it and none coming in, while another node will have three currents entering it and none leaving. The only way I can think of that happening is if all the currents are equal to zero, but surely this is not the answer...... Anyway, the only other work I could do was to note that the 10Ω and 5Ω are in parallel, so i2 = 2i1. Also, the current source is producing 9A, since the supplied current is supposed to be VΔ/2, but that doesn't seem to help my situation much.