# Homework Help: Circuit Design

1. Dec 6, 2011

### wany

1. The problem statement, all variables and given/known data
You have two clock signals (one is 25/sec,other is 30/sec).
Design a circuit that takes both clocks as inputs, determines the faster one within a second, and indicates faster one by lighting an led. The led should remain on until reset by a control signal.
You may use AND, OR, and NOT gates, SR latches, T-FF's and
D-FF's, LEDs, resistors, and switches; don't try doing this with analog filters.

2. Relevant equations
Can use AND, NOT, OR gates, SR latches, T-FF's, D-FF's, LEDs, resistors, and switches

3. The attempt at a solution
Im having a hard time on this one. I was maybe thinking that pass each of them through a separate binary counter. Thus after a second, one should read 11110 the other 11001. Then once it has been a second, a switch closes and reads say the last digit of each number. If it is a zero, then that led should be lit. If not then it shouldnt be lit. So once this switch closes, both should be fed to some sort of memory latch that will hold this value until the reset control signal is initiated. Thus, then the two outputs of the memory latch will be passed through a NOT gate and then fed to a resistor/led. THus the one with a 0 will have the led lit.

I am not sure if this will work/ is correct. Also, I do not know if we can even use a switch that closes after a second. Any help would be appreciated.

2. Dec 6, 2011

### Staff: Mentor

Creating a couple of 4 or 5 bit counters is heading for a complicated solution, including probably having to construct a third one to count say, 25 counts, so you can mark the passage of time. I think you should try for a simpler solution first, and leave the complicated one until all other options have been exhausted.

No I haven't worked out an alternative solution; I just have a feeling that multiple counters is not the way to solve what is, on the face of it, a simple digital task.

3. Dec 6, 2011

### wany

Ya that makes sense since my way did seem very complicated to myself. So just thinking, we know that one pulse is faster than the other. But I am stuck from here.

4. Dec 6, 2011

### Staff: Mentor

Are you going to design this entirely on paper, or are you able to build up a simulation in stages, testing each piece as you progress?

5. Dec 6, 2011

### wany

Entirely on paper.

6. Dec 6, 2011

### Staff: Mentor

There's sure to be an online digital circuit simulator; may be worth searching for one. There is probably free software you can run on your PC, too. Alas, I'm not of much help here.

7. Dec 6, 2011

### wany

Ya Ill look into that. I still am not sure where to head with this problem though.

Also thank you for your help.

8. Dec 7, 2011

### Staff: Mentor

Summarizing your proposed method so far: start a pair of n-bit counters simultaneously, when a MSB (most significant bit) turns 1 that indicates the fastest clocking counter. Writing it this way makes it sound more streamlined than I first pictured it. (The hint in the question, about allowing a second for processing, would tie in with this.)

I think you should work on this, see whether you can make it work.

9. Dec 7, 2011

### skeptic2

Hah! In 1995 I designed that circuit into a product using nothing more than those components. The solution is far simpler than you what you have suggested.

I can lead you to the solution but you have to do the work. Most importantly, you have to understand how each of the components works and how the function of particular components can contribute to the design solution.

To start, what would the outputs of an RS Flip Flop look like if you fed one pulse train into one input and the other one into the other input? Is there any asymmetry in the output waveform that could give a clue as to which input has the higher frequency?

10. Dec 7, 2011

### wany

If we fed both of them to an RS flipflop the output would be something like:

The truth table is
C1...C2...Q...Q*
0.....0.....Q...Q*
1.....0.....0...1
0.....1.....1...0

Therefore say C1 is the faster clock. Then the output of Q would be zero until C2 is high which happens less frequently than Q* being high. Therefore, depending on whether Q is high or low most of the time, we can determine which is the faster clock. Is this correct?

11. Dec 7, 2011

### skeptic2

If C1 is the faster clock, then Q will alternate high and low except that once every 6 C1 cycles there will be 2 C1 positive going edges without a positive going edge from C2 between them. This results in an extra long positive pulse on Q* which indicates that C1 has the higher frequency. There never is an extra long positive pulse on Q. This method should give you the higher of the two frequencies in a maximum of 0.2 seconds.

Question: how do you trap that extra long positive pulse on Q* and use it to indicate the higher frequency?

12. Dec 7, 2011

### wany

Ok the top part makes sense. I did the calculations and I see that what you say makes sense.

Now Ive been thinking about your question but just cant picture anything that would be able to do that. Would we need some type of comparator?

13. Dec 7, 2011

### wany

I was thinking that a small enough capacitor would do the job, but capacitors were not listed in the possible tools at our disposal.

14. Dec 7, 2011

### skeptic2

When you get two rising edges on the C1 input without an intervening rising edge on the C2 input, the Q* will already be high when the second C1 rising edge arrives. That will never happen with the slower pulses. Suppose you were to run a line from C1 to the clock input of one of the flip flops and connect the Q* to another one of the inputs of the same flip flop to latch the positive output of the Q*. Which one of the flip flops would work the best for that?

The same circuit should be connected to the C2 side of the RS flip flop in case C2 happens to be the higher frequency pulses.

Can you compute the outputs of both of the latching flip flops connected to the RS flip flop? What do you notice about them.

Before I first replied to this thread, I tested this circuit using LT Spice. If you're not familiar with SPICE you should become familiar with it. LT Spice is free and not limited in any way. A lot of problems on this board are illustrated with it. Once you learn to use it, it can really help you in school. Analyzing this circuit for instance is a lot easier than trying to figure out truth tables.
http://www.linear.com/designtools/software/#LTspice

15. Dec 7, 2011

### cmb

What's the nature of the signal? A pico-second spike, a 50% duty cycle pulse.. or??..

16. Dec 7, 2011

### wany

Alright let me see if I understand this correctly so far.

So use C1 and C2 as the inputs of an SR latch. Then feed C1 and Q* to a latch and C2 and Q* to another latch.

Would we want these two latches to be D flip-flop then since the output takes the value of the input that was present just prior to the triggering clock transition.

So our circuit would be feed C1 and C2 to an SR latch. Then feed C1 and Q* to a D flip-flop and C2 and Q* to a D flip-flop.

17. Dec 7, 2011

### wany

Also, I do have spice, and have tried to use it but still having trouble. The two clock signals are pulses. 25 pulses/second; 30 pulses/second for the other one

18. Dec 7, 2011

### skeptic2

Yes, C1 & Q* would go to the clock and D input of a D flip flop. C2 & Q, not Q*, would go to the second D flip flop clock and D input respectively. Note that for 5 out of 6 of the C1 pulses will result in a low output from the D flip flop. Only 1 out of 6 will give you a high output. The important thing is that out of the other D flip flop there will never be a high output because there can never be two of the slower pulses without an intervening faster pulse on the other input.

So now all you have to do is run the outputs of both D flip flops into another latch that will latch the high level from whichever input is feeding positive pulses. Both outputs of that latch would be connected to LEDs to indicate which output is high. What is the type of latch you would need to latch the occasional high pulse from the D flip flop?

19. Dec 7, 2011

### wany

Oh ya it would be Q and not Q*. I keep forgetting we dont know which clock has the faster pulse, so I guess that is messing me up a little.

Alright so Im thinking about this. So we know that one output of the D flip-flop will never be high. Thus it will always be a 0. The output of the other D flip-flop will be high occasionally. Thus we would want a latch that stayed the same after the high output changed to a low and back to a high.

Thus wouldnt we just feed both the outputs of the D flip-flops to a SR latch?

Because we know that when S is 1 and R is 0, Q is 1 and Q* is 0. When S is 0 and R is 0, the states of Q does not change.

20. Dec 7, 2011

### skeptic2

SR latch is correct.

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