# Homework Help: CMOS circuit

1. Oct 11, 2009

### ╔(σ_σ)╝

I'm doing some reading about CMOS circuits and the likes. In the book I'm using it tells me to derive the simplest sum of products for an expression from a truth table.

The canonical sum of product is as follows:
*- AND
!- NOT
+ - OR

(!x1*!x2* !x3*!x4) + ( !x1*x2*!x3*!x4) +(x1*!x2*!x3*!x4) = f

Using Boolean algebra I was able to simplify to

(!x2*!x3*!x4) + (!x1*!x3*!x4)= f which is the simplest sum of products.

Then the book then asks how many transistors are needed to implement the sum of products circuit using CMOS AND,OR,and NOT gates.

My solution was as follows:

We need :

2 -3input CMOS AND gates => 2(4*2) transistors = 16 transistors
4- CMOS inverters => (4*2) transistors = 8 transistors
1- 2 input CMOS OR gate => 1(3*2) transistors =6 transistors

16+8+6 = 30 transistors

But the answer is 28 transistors i'm not sure what I'm doing wrong.

I realize that 8 transistors are used to implement CMOS 3input AND gate, 2 transistors are needed for CMOS 1input inverter and 6 transistors for 2input OR gate.

What I'm I doing wrong ?

2. Oct 11, 2009

### ╔(σ_σ)╝

Does anyone know what I'm doing wrong ?

3. Oct 11, 2009

### swuster

Simplify your AND and OR gates to NAND and NOR gates - those 2 extra transistors are probably accounted for by eliminating a NOT gate somewhere.

4. Oct 11, 2009

### ╔(σ_σ)╝

But the question specifically says to use AND, OR and NOT gates no NAND and NOR gates.

5. Oct 11, 2009

### uart

It's fairly standard practice to simplify boolean logic to a sum of products form but then to implement it in a "Nand-Nand" form. Note that by Demorgans Law "And-Or" is directly equivalent to "Nand-Nand".

I'm not really sure if that's what your question wanted but just pointing it out.

6. Oct 12, 2009

### uart

ok the above was a "generic" response made without looking in detail at the logic function involved. I just took a more detailed and yeah you can do it with 28 transistors and using only "and" "or" and "not" gates.

For a straight forward two level implementation I got the following.

SOP with AND/OR implementation : 30 transistors (same as OP).
SOP with NAND/NAND implementation : 26 transistors.
POS with NOR/NOR implementation : 10 transistors (this is a pretty efficient implementation).

Here's a hint. The above is for a "two level" implementation. Do some simple boolean algebra (factorization) on the minimized SOP form and you can cut it down to a 28 transistor AND/OR implementation.

7. Oct 12, 2009

### ╔(σ_σ)╝

(!x2*!x3*!x4) + (!x1*!x3*!x4)

I tried factoring and I got

(!x3*!x4)(!x2+ !x1)=f

Which means I need
2- 2 input AND gates
4- inverters
1- 2 input or gate

Which gives me 26 transistors not 28.

Can you be more clear cause I'm not sure how you can get 28. I keep getting 26 or 30 with AND,OR and NOT gates (all three).

8. Oct 12, 2009

### uart

Whoops yeah you're right it's only 26. (I was just figuring the whole thing out in my head when I got 28 ).

Anyway there's nothing wrong with that working, if you can do it in 26 then that's a better solution than the books. I'm not sure if the author had another solution in mind or if it's a simple error on their part. Maybe they're like me and just cant add up.

9. Oct 12, 2009

### ╔(σ_σ)╝

Okay thanks mate.

I guess it wasn't an error on my part.