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CMOS EE help.

  1. Nov 19, 2008 #1
    1. The problem statement, all variables and given/known data
    Here is an image of the problem (Write the circuit in min SOP form.) http://img211.imageshack.us/my.php?image=ddtl0.jpg

    2. Relevant equations

    3. The attempt at a solution

    I've looked at it and gone over notes but I don't get it. If you would like I can scan my sheet of scribblings on there but they're all uneducated attempts to solve this.
  2. jcsd
  3. Nov 20, 2008 #2
    Ok, I went through it and I think that it's one big NAND. so the min sop is NAND(A&B&C)

    Any confirmation?
  4. Nov 20, 2008 #3


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    Staff: Mentor

    So what's your equation for the output in terms of A, B, C? Show us your K-map.
  5. Nov 20, 2008 #4
  6. Nov 20, 2008 #5


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    Staff: Mentor

    I think I see an error in ABC~ in the first equations... And you need a pull-down on the first circuit to make it meaningful. Please re-check the tables to see if I'm making an error....
  7. Nov 20, 2008 #6
    Ok, so I re-did this problem and got ~C as the final answer. I'm pretty confident that that's the right answer, but please confirm :-p


    Ok, re-did it again and got (A&~B) | (~A&B) | (B&~C) | (~B&~C)

    More confident this time around :-p
    Last edited: Nov 20, 2008
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