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Computer Architecture Help

  1. Nov 16, 2004 #1
    Hello. I need some help with this question involving Pipelines. Any help would definatley be appreciative.

    Why is the PC (Program Counter) is incremented by 4 for a superscalar pipeline which executes TWO instructions at a time

    Thanks in Advance!
  2. jcsd
  3. Nov 17, 2004 #2
    What architechture ?
  4. Nov 18, 2004 #3
    MIPS assembly language
  5. Nov 20, 2004 #4
    In MIPS, the program counter counts instructions in "bytes" instead of "instructions". In most implementations, PC<--PC+1 would move to next instruction but in MIPS, PC<--PC+1 moves to next byte.

    In MIPS , each instruction is of fixed length of 32 bits or 4 bytes, which probably explains your question.

    -- AI
  6. Nov 21, 2004 #5
    That seems pretty logical. If MIPS is a 16-bit machine its "words" would consist of two bytes, so it has to skip ahead 2 per instruction and not 1.
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