Computer Architecture Help

  • Thread starter Jusamyth
  • Start date
2
0
Hello. I need some help with this question involving Pipelines. Any help would definatley be appreciative.

Why is the PC (Program Counter) is incremented by 4 for a superscalar pipeline which executes TWO instructions at a time

Thanks in Advance!
 
293
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What architechture ?
 
2
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MIPS assembly language
 
644
1
In MIPS, the program counter counts instructions in "bytes" instead of "instructions". In most implementations, PC<--PC+1 would move to next instruction but in MIPS, PC<--PC+1 moves to next byte.

In MIPS , each instruction is of fixed length of 32 bits or 4 bytes, which probably explains your question.

-- AI
 
293
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That seems pretty logical. If MIPS is a 16-bit machine its "words" would consist of two bytes, so it has to skip ahead 2 per instruction and not 1.
 

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