Confused how do you calculate propagation delay of circuit and paths?

In summary, the conversation discusses how to calculate propagation delay of a circuit and its paths. The formula for propagation delay through a gate is given as .04+.014*SL, where SL is the sum of standard loads. To find the total propagation delay for a path, the delays of each gate in that path must be added. The maximum delay should be considered when accommodating for propagation delay. Different input conditions may result in different propagation delays, so it is important to test all possible combinations.
  • #1
mr_coffee
1,629
1
confused! how do you calculate propagation delay of circuit and paths?

Hello everyone, this book explains literally nothing about propgatation delay and how to calculate propagation delay of gates and the paths. And yet one of the questions says:
http://img226.imageshack.us/img226/7273/lastscan7tl.jpg [Broken]
I found propagation delay of somthing but i don't know what...
I looked up the Input load of a 2NAND gate and it said 1.00.
Then I saw its formula listed in the table as:
.04+.014*SL; SL is the sum of standard loads. So if there is 5 2NAND gates, it would be SL = 5*1.0 = 5 right?
Then tpd = .05+.014*5 = .12ns;
But the question gives me values of T_PHL = .30ns, and T_PLH = .50ns, so i have n oidea what i found above, and i don't know if it was finding the tpd of the gates or of the paths? Thanks. any help would be great!
 
Last edited by a moderator:
Physics news on Phys.org
  • #2
tPD is just the propagation delay through a gate. If it is different for low-high versus high-low (that's the transition direction at the input), then the two different numbers are given, tpLH and tpHL.

To find the propagation delay for each path, you will add each gate's contribution to get the total. It may be different for the HL and LH input conditions. In general, you want to find the max delay, because that is what you will have to accommodate. So for each path from A,B,C,D to F (assuming that the inverted versions of the inputs are available as shown in your scan), toggle one input LH or HL, and see what happens at the output. Some paths may get blocked by the logic terms, and not propagate to F.

So for example, set A=0 and that blocks off the top paths' influence on the final output gate. Set C- = 1 to enable the bottom input gate's path. Then as you raise B low-high, you get one tpLH through that first gate, but the output gate is held off and the signal doesn't make it through. Now come up with a combination of the inputs that puts a 1 at the top input of the output gate, and then when you raise B low-high, you get a tpLH from the first gate and a tpHL from the output gate for that path. Then lower B high-low, and you get a tpHL from the input gate and a tpLH from the output gate.

Mess with different input codes to get signals to propagate down each path, and list all the total end-to-end delays. Make sense?
 
  • #3


Hello there,

I understand your confusion about calculating propagation delay of circuits and paths. Propagation delay is the amount of time it takes for a signal to travel from the input of a gate to the output of that gate. It is also the time it takes for a signal to travel along a path from one point to another in a circuit.

To calculate the propagation delay of a gate, you can use the formula provided in your book: tpd = 0.04 + 0.014*SL. SL stands for standard loads, which can be calculated by multiplying the input load of the gate by the number of gates in the circuit. This will give you the total input capacitance of the circuit.

To calculate the propagation delay of a path, you can use the same formula, but instead of using the input load of a gate, you would use the input capacitance of the entire path.

In the example question you mentioned, it seems like the values for T_PHL and T_PLH are already given, so you don't need to calculate them. However, if you want to verify the values given, you can use the above formula to calculate the propagation delay for each gate and then add them together to get the total propagation delay for the path.

I hope this helps clarify the concept of propagation delay and how to calculate it for gates and paths. If you have any further questions, please don't hesitate to ask. Best of luck!
 

1. What is propagation delay and why is it important in circuit design?

Propagation delay is the amount of time it takes for a signal to travel through a circuit or path. It is an important factor in circuit design because it affects the overall speed and performance of the circuit. A longer propagation delay can result in slower signal transmission and can cause timing issues in digital circuits.

2. How do you calculate propagation delay?

The propagation delay can be calculated by dividing the length of the path by the propagation speed. The propagation speed is dependent on the type of medium the signal is traveling through, such as copper wires, optical fibers, or air.

3. Is there a difference in propagation delay for different types of signals?

Yes, there can be a difference in propagation delay for different types of signals. Analog signals typically travel at a constant speed, while digital signals can have varying propagation speeds depending on the circuit components and design.

4. How can propagation delay be reduced in a circuit?

Propagation delay can be reduced by using shorter paths, optimizing the placement of components, and using faster transmission mediums. Additionally, advanced circuit design techniques, such as pipelining and parallelism, can also help reduce propagation delay.

5. Can propagation delay be completely eliminated in a circuit?

No, it is not possible to completely eliminate propagation delay in a circuit. However, it can be minimized through careful design and optimization to improve circuit performance.

Similar threads

Replies
10
Views
3K
  • Quantum Physics
Replies
4
Views
3K
Replies
1
Views
1K
  • Introductory Physics Homework Help
Replies
5
Views
2K
Replies
4
Views
3K
Back
Top