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Homework Help: Confused how do you calculate propagation delay of circuit and paths?

  1. Oct 23, 2005 #1
    confused!! how do you calculate propagation delay of circuit and paths?

    Hello everyone, this book explains literally nothing about propgatation delay and how to calculate propagation delay of gates and the paths. And yet one of the questions says:
    http://img226.imageshack.us/img226/7273/lastscan7tl.jpg [Broken]
    I found propagation delay of somthing but i don't know what...
    I looked up the Input load of a 2NAND gate and it said 1.00.
    Then I saw its formula listed in the table as:
    .04+.014*SL; SL is the sum of standard loads. So if there is 5 2NAND gates, it would be SL = 5*1.0 = 5 right?
    Then tpd = .05+.014*5 = .12ns;
    But the question gives me values of T_PHL = .30ns, and T_PLH = .50ns, so i have n oidea what i found above, and i don't know if it was finding the tpd of the gates or of the paths? Thanks. any help would be great!!
    Last edited by a moderator: May 2, 2017
  2. jcsd
  3. Oct 24, 2005 #2


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    Staff: Mentor

    tPD is just the propagation delay through a gate. If it is different for low-high versus high-low (that's the transition direction at the input), then the two different numbers are given, tpLH and tpHL.

    To find the propagation delay for each path, you will add each gate's contribution to get the total. It may be different for the HL and LH input conditions. In general, you want to find the max delay, because that is what you will have to accommodate. So for each path from A,B,C,D to F (assuming that the inverted versions of the inputs are available as shown in your scan), toggle one input LH or HL, and see what happens at the output. Some paths may get blocked by the logic terms, and not propagate to F.

    So for example, set A=0 and that blocks off the top paths' influence on the final output gate. Set C- = 1 to enable the bottom input gate's path. Then as you raise B low-high, you get one tpLH through that first gate, but the output gate is held off and the signal doesn't make it through. Now come up with a combination of the inputs that puts a 1 at the top input of the output gate, and then when you raise B low-high, you get a tpLH from the first gate and a tpHL from the output gate for that path. Then lower B high-low, and you get a tpHL from the input gate and a tpLH from the output gate.

    Mess with different input codes to get signals to propagate down each path, and list all the total end-to-end delays. Make sense?
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