Converting Mips to binary

1. Jan 31, 2011

Hey Guys!!!! Thank you for checking out my Thread.... I am taking a computer assembly class and i have homework due on Wed but i am stuck on a single problem. I have to convert MIPS instructions into binary, I want to learn how to do this because it will be on a test... and i could just go into mars and assemble the code and read it from there but i wanna know how to do it..... okay soo the instructions are:
addi $sp,$sp, -8
sw $ra, 4($sp)

Now from looking into my book i see that addi has an Opcode of 001000 and it has a I instruction format...
Also sw has an Opcode of 101011 and is an I instruction format

How do i figure out what registers $sp?,$ra, the array 4($sp) are in binary? Please help... i would really appreciate it! 2. Jan 31, 2011 Mark44 Staff: Mentor See http://en.wikipedia.org/wiki/MIPS_architecture, in the section titled Compiler register usage.$sp is the stack pointer, and its value in MIPS instructions is $29.$ra is return address; its value is $31. 4($sp) would be an address on the stack - $sp + 4*(size of a machine word). Here's another link to a site that lists the instructions and what they look like in binary - http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html. For your ADDI instruction, the constant to be added is -8, which will need to be written in two's complement form. 3. Jan 31, 2011 basketball853 Thank you for your reply... i have already checked those sites out... but they have not helped me at all.... So how do i go about converting it into binary code? i think i am missing the simple concept... So i take Addi for instance and use its opcode... okay cool got that done but what about the registers? all it says on that web site is: Used to add sign-extended constants (and also to copy one register to another: addi$1, $2, 0), executes a trap on overflow 001000ss sssttttt CCCCCCCC CCCCCCCC what the hell does that mean lol 4. Jan 31, 2011 Mark44 Staff: Mentor This -001000ss sssttttt CCCCCCCC CCCCCCCC - shows how the instruction op code and registers and operands are encoded to make up an ADDI instruction. First 6 bits - the instruction opcode (001000 for ADDI) Next 5 bits - the source ($2 in your example)
Next 5 bits - the destination ($1 in your example) Next 16 bits - the immediate value ADDI effectively does this$t = $s + imm. value So if you wanted to add 5 plus the value in$t1 to $t2, the MIPS assembly instruction would be: ADDI$t2, $t1, 5 Note that the numbers associated with$t0 and $t1 are 8 and 9. The binary form of this instuction would be Code (Text): 001000 01001 01000 0000000000000101 opcode ......|$t1..|
............| $t0.| ..................|........5.............| 5. Jan 31, 2011 basketball853 Thank you again for clarifying that...but what if there is no value for the registers i see that i have a constant of -8 which i would use two's complement but for the other$sp register is it defaulted at 0?

6. Jan 31, 2011

Staff: Mentor

Are you asking about ADDI $sp,$sp, -8?

What do you mean "but for the other $sp register is it defaulted at 0" 7. Jan 31, 2011 basketball853 Yes i am addi$sp, $sp, -8 would that in the end turn to be (opcode) 001000 (default 0 for$sp) 00000 (default 0 for $sp) 00000 1111111111110111 (-8) 8. Jan 31, 2011 Mark44 Staff: Mentor 0 is not the number for$sp, so the parts with 00000 and 00000 are not right. This link - http://en.wikipedia.org/wiki/MIPS_architecture- tells you the numbers of all the registers. I also told you what it was in post #2.

9. Jan 31, 2011

oohhh i think i may understand.... so the value of $sp ( the stack pointer) is$29 sooo
it would be

001000 11101 11101 111111111111011
opcode $sp$sp -8 constant

did i correctly get the value?

10. Jan 31, 2011

Staff: Mentor

Looks good!

11. Jan 31, 2011

okay SWEET!!! soo and for the other one i got
101011 11111 11111 how do i figure out the 4($sp) ? you stated before "4($sp) would be an address on the stack - $sp + 4*(size of a machine word)." so do i take 29 + 4 * ( idk what the size of word is) ? 12. Feb 1, 2011 Mark44 Staff: Mentor sw$ra, 4($sp) What this is doing is to store the word (== 32 bits) at$sp + 4 to the $ra register. The size of a machine word seems to be 32 bits, since that's the size of the encoded instruction. Let's go with that assumption. According to the reference I cited, the encoded instruction is 101011 sssss ttttt iiii iiii iiii iiii. Here, the s bits hold the source register, the t bits the destination register, and the i bits the offset from the source register. I am thinking now that the offset is in bytes, so we use the offset as-is. So the number for$sp is $29, the number for$ra is $31, and the offset is 4. I think this is the encoded instruction for SW$RA, 4($SP) 101011 11101 11111 0000 0000 0000 0100 The first 6 bits are the SW instruction. The next 5 bits are the source register,$SP. The next 5 bits are the \$RA register, and the last 16 bits are the offset, which is 4.

13. Feb 1, 2011

Thank you so much for your help!! You have really helped me understand this!! I am very grateful!!!!

14. Feb 1, 2011

Staff: Mentor

You're very welcome. Thanks are always appreciated!