I'm trying to create a code in verilog that needs to use counters so it can preform specific actions during certain clock cycles.
I believe that these lines of code need to be used
counter <= 0;
counter <= counter +1;
The Attempt at a Solution
How to use those lines of code, I don't know. I know that reg[3:0] counter; must be declared with the inputs and outputs. Where the other 2 get declared though, I haven't a clue.