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Counters in verilog

  1. Dec 2, 2009 #1
    1. The problem statement, all variables and given/known data
    I'm trying to create a code in verilog that needs to use counters so it can preform specific actions during certain clock cycles.


    2. Relevant equations
    I believe that these lines of code need to be used

    reg[3:0] counter;
    counter <= 0;
    counter <= counter +1;

    3. The attempt at a solution
    How to use those lines of code, I don't know. I know that reg[3:0] counter; must be declared with the inputs and outputs. Where the other 2 get declared though, I haven't a clue.

    Thanks
     
  2. jcsd
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