# D and JK Flip Flops

1. Apr 22, 2013

### Xyius

Hey Everyone,

I am just starting now to REALLY get into digital circuits and I am trying my hardest to learn about Flip Flops via the internet. What I am finding is a horrible amount of inconsistencies and it is confusing me! First I started here..

http://computer.howstuffworks.com/boolean4.htm

One inconsistency I found is that he says r=1 and s=1 is not allowed and r=0, s=0 remembers, but EVERYWHERE else I read it says the opposite!

Then I moved on to the JK flip flops. (same article)
I quickly realized that this article does NOT use the standard symbol for the JK flip flop. I am trying to match together all these inconsistencies. So this is what I understand..

In a normal JK flip flop symbol..
S(or the top pin) means "Preset" which I am unsure of what that exactly means.
R(or the bottom pin) means "Clear"
And the triangle symbol means clock.
J and K are the parameters used to control the output Q and Q'.

I also noticed that the truth tables from different sources were different. Why is it that some of the tables don't include "Preset" or "Clear"?? The table from "How stuff works" includes the clock signal, but the table from wiki does not it has a "comment" and a "Qnext" which I do not know what that means.
http://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop

Then I tried opening a circuit simulator any messing around with the JK flip flop and I couldn't replicate ANY of the things it talks about in the "How stuff works" article. I also tried looking to other sources but I haven't had too much time yet to go through these sources in detail.

If anyone can help me out and clear some of this up it would be most appreciated!

2. Apr 23, 2013

### carlgrace

I think the website is using active low logic, which is why you're so confused. Typically the S=1, R=1 is illegal in an SR flip flop. JK is the same flip flop except that S=1, R=1 "jams" the flip flop and causes it to toggle.

You'd probably be better off reading a textbook on Logic Design rather than wading through a bunch of websites, although the Wikipedia article is pretty good.

3. Apr 23, 2013

### Xyius

Do you have any good books to recommend?

4. Apr 24, 2013

### Jony130

Well we can treat RS flip-flop as a "black box" or we can use a logic gate to build RS flip-flop.
When we treat RS flip-flop as a "black box" we use this symbol

But we can all so use a logic gate to build RS FF. And we can use NOR and NAND gates.

So as you can see for NOR gate RS FF the "idle state" is LOW and for NAND gate the "idle state" is HIGH.

For NOR RS we need a logic 1 at "SET" input to make a Q output rise to a logic 1 level.
And we need a logic 1 at "RESET" input to make a Q output back to a logic 0 level.
So we can say that NOR RS flip-flop is a active high device (active high means function gets done when input is in high state).

And NAND RS flip-flop is a "active low device".
We need a logic 0 at "SET" input to make a Q output rise to a logic 1 level.
And we need a logic o at "RESET" input to make a Q output back to a logic 0 level.

I hope that now you can see the difference between RS FF

Normal JK flip-flop looks like this

And this JK has a "synchronous" inputs, a clock trigger flip flop.
Inputs have control over the flip-flop's outputs only when the clock pulse allows.

But some time we can see this type of a JK flip-flop.

And this JK flip flop act just like a normal JK plus additional RS flip-flop.
Asynchronous inputs (SET or RESET) force the outputs state independent of the clock input.
This RS inputs have a higher priority than the clock input.

#### Attached Files:

• ###### RS.PNG
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5. Apr 24, 2013

### Xyius

Thank you SO MUCH Jony!! You have cleared everything up for me! :D!

6. Apr 24, 2013

### carlgrace

Fundamentals of Logic Design is a classic in the field, and it isn't at too high a level. The older editions are cheap and still very valuable since the fundamentals haven't changed much in years. The fourth edition is the one I studied in school and is just a couple of bucks now.