# D Flip Flop with enable

1. Nov 24, 2012

### torino

1. The problem statement, all variables and given/known data
What does flip flop with clock enable mean and what is the next state equation for D flip flop with clock enable?

Last edited: Nov 24, 2012
2. Nov 24, 2012

### lewando

The clock enable is used to freeze the state of the flip-flop when "not enabled". When "enabled", the flip-flop acts normally. Avoid asynchronous assertion/de-assertion of this input for best results. See datasheet for a 74377 for more information.

3. Nov 24, 2012

### torino

Can you please explain what do you mean by this ?

4. Nov 24, 2012

### lewando

I just mean when you affect the operation of a digital system by means of using a clock enable or otherwise gating the clock, it's a good idea to make sure you are doing so in a controlled manner (unless the consequences of not doing so are inconsequential). If you were to disable the f-f by de-asserting the clock enable signal around the same time the falling edge (typically the edge that makes the f-f update its state) was happening, you have some uncertainty as to which occurs first (and so uncertainty of the state of the f-f: updated or not updated). To reduce this uncertainty, control when the clock enable changes state. This means synchronize the clock enable with the clock, ideally using the rising edge of the clock (when the f-f is not being updated) to do the synchronization. Hopefully this is clear. Ask away if not.

Last edited: Nov 24, 2012
5. Dec 1, 2012

### torino

Thanks for the clarification. I drew a circuit for the d flip flop with clock enable. I just connected an AND gate to the flip flop with two inputs (clock and enable) Is it correct?? and for the characteristic equation i'm still not sure how to get it. Should i make a truth table with four values (D,Q,E(enable),C(clock)) and an output (Q+). I did that but I don't think it's correct. I've been told that the value of E(eneable) shouldn't change in the truth table. I just change the values of D,Q,C.