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Data transmission with counter

  1. Oct 7, 2009 #1
    Hi!

    I want to design a data transmission circuit (transmit 7 bits data with 1 start, stop, and parity bit) by using gates.

    The part I have done is CRC and parity.Now I want to design the transmission part, I want to use a counter to count the time of data division until 8 then transmit the remainder from CRC to do the parity.So where can I connect the counter to my circuit?

    I am using 74175(IC) to register the CRC code, 74165 to load the 7 bits of my data into the system, two 7483 for adding (process of 2 complement), one 74194(data load from 7475 if the adder output is positive value,if not the 74165 will shift data into it), and one 7475(store data of the remainder).

    When the 7 bits all have transmitted to the adder and the 7475 output data stopped changing, I want to transmit it to parity part.So I need one counter to count until 8( make sure the data of the remainder is in final state )Where should my counter connect?

    For transmission, initially I need to transmit 11 empty bits first to the receiver, how can I do it?because when my circuit clock is on, my data will load into the circuit.

    Thanks!
     
  2. jcsd
  3. Oct 7, 2009 #2

    berkeman

    User Avatar

    Staff: Mentor

    Show us your work so far. This is obviously homework, but I'll let it stay here in EE if you show us in detail what you've done, and what part you're having trouble with. We can offer tutorial help, but will not do your schoolwork for you.
     
  4. Oct 8, 2009 #3
    Thank you!

    I have work out the circuit of division. I choose 74194 to insert 4 bits data from the latch ( the remainder of each part in the division process). 74165 as the shifting ( the output of the 74165 is connected to 7483 adder and 74194 ). 74175 as the register of CRC-3bit( I have chosen 1011 for the CRC-3bits data) and connected to 7483 adder.7483 is coonected to 7475 latch and ANDing clock and the (cout) of the 7483 to active the latch. The division process that I used is 2 complement addition.Clock is connected to all the IC.

    Am I make you clear now?

    My problem is I don't know how to control the 74165 IC's clock, the 1st value that I insert in this IC can be shifted to the right, but start from the second value, it cannot shift to right.Although the pin (synchronous Parallel Load Input) has set to high.Can anyone help me solve it?

    To complete the CRC, I need to get the final remainder to divide with the original 7 bits data, so I need to count until 8 for the clock(each clock 1 bit data is shifting in) so how to create a conter like that?

    Next is during transmission. I need to make the system to send 11 bit empty bits first, I have no idea how to pulse my CRC system when the system started.

    I hope you can give me some advise to do my project.
     
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