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Decoder glitches

  1. Mar 6, 2012 #1
    Hello all,
    I have a lab this afternoon that I was going over to ensure I was prepared for it. However, I am not entirely sure about the last part of the lab. Any help or reassurance is appreciated!

    Decoder Glitches- Use a 3 input AND function to detect the logic state corresponding to "6" in binary (Q8=1, Q4=1 and Q2=0). Use a logic analyzer to display the expected output and the very brief "glitch" that occurs at the beginning of the zero state.

    I'm looking for reassurance as to the first part. I have decided to use a frequency divider utilizing D flip flops, an inverter and an AND gate. Attached is my photo. The AND gate outputs 1 when Q8Q4Q2'=110, which is six.


    Attached Files:

  2. jcsd
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