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**designing a two-bit adder using verilog's primitive gates_I get "z" for my outputs**

Hi,

I am trying to write verilog code for a two bit adder using verilog's primitive gates. I had implemented a two bit adder before...using gates I myself had implemented with nmos and pmos transistors, with delays of 3,4,5 (ns) for the nmos transistors and 5,6,7 (ns) for the pmos transistors. The worstcase delay I had calculated for the final adder was 31 ns.(I think we need to know this to get good results when simulating!) And I had instantiated this adder within a testbench. When I simulated my adder, I didn't have any problems.

Here are the code I used for the adder and the testbench of the adder:

(mxor/mnand2/mnand3/minverter used below, are my own gates that I had implemented and tested each; and they all worked fine!)

************************************************************

module madder(input a1,a0,b1,b0, output s2,s1,s0);

wire nanda0b0,notnanda0b0,xora1b1,nanda0b1b0,nanda1b1,nanda1a0b0;

mxor xorfors0(a0,b0,s0);

mnand2 nand2fors1(a0,b0,nanda0b0);

minverter inverterfors1(nanda0b0,notnanda0b0);

mxor xor1fors1(a1,b1,xora1b1);

mxor xor2fors1(xora1b1,notnanda0b0,s1);

mnand3 nand31fors2(a1,a0,b0,nanda1a0b0);

mnand2 nand2fors2(a1,b1,nanda1b1);

mnand3 nand32fors2(a0,b1,b0,nanda0b1b0);

mnand3 nand33fors2(nanda1a0b0,nanda1b1,nanda0b1b0,s2);

endmodule

*********************************************************

module madderTester();

reg ia1=1;

reg ia0=1;

reg ib1=1;

reg ib0=1;

wire ws2;

wire ws1;

wire ws0;

madder madderInstance(ia1,ia0,ib1,ib0,ws2,ws1,ws0);

initial repeat(50) #72 ia1=~ia1;

initial repeat(45) #61 ia0=~ia0;

initial repeat(40) #79 ib1=~ib1;

initial repeat(50) #67 ib0=~ib0;

endmodule

****************************************************************

Now I'm supposed to implement the same two bit adder using verilog's primitive gates.

I have calculated the worst-case delays of each gate (2-input nand/3-input nand/nor/xor/not), using the same numbers as above (3,4,5) and (5,6,7) for nmos and pmos transistors respectively. Using these time delays and the transistor implementation of each gate, I have calculated 0-to-1 and 1-to-0 delays for each of the above gates that I need in my two bit adder.

These are the delays I found: (the first delay is 0-to-1 delay and the second one is 1-to-0)

*for 2-input nand: 7; 10 (ns)

*for 3-input nand: 7; 15 (ns)

*for xor: 21; 24 (ns)

*for not: 7; 5 (ns)

Here's my code for the two bit adder using verilog's primitive gates (and the gate delays I calculated above):

*******************************************************

module madder(input a1,a0,b1,b0, output s2,s1,s0);

wire nanda0b0,notnanda0b0,xora1b1,nanda0b1b0,nanda1b1,nanda1a0b0;

xor #(21,24) xorfors0(a0,b0,s0);

nand #(7,10) nand2fors1(a0,b0,nanda0b0);

not #(7,5) inverterfors1(nanda0b0,notnanda0b0);

xor #(21,24) xor1fors1(a1,b1,xora1b1);

xor #(21,24) xor2fors1(xora1b1,notnanda0b0,s1);

nand #(7,15) nand31fors2(a1,a0,b0,nanda1a0b0);

nand #(7,10) nand2fors2(a1,b1,nanda1b1);

nand #(7,15) nand32fors2(a0,b1,b0,nanda0b1b0);

nand #(7,15) nand33fors2(nanda1a0b0,nanda1b1,nanda0b1b0,s2);

endmodule

*************************************************************

And the testbench:

module madderTester();

reg ia1=1;

reg ia0=1;

reg ib1=1;

reg ib0=1;

wire ws2;

wire ws1;

wire ws0;

madder madderInstance(ia1,ia0,ib1,ib0,ws2,ws1,ws0);

initial repeat(50) #31 ia1=~ia1;

initial repeat(45) #47 ia0=~ia0;

initial repeat(40) #81 ib1=~ib1;

initial repeat(50) #73 ib0=~ib0;

endmodule

********************************************************

When I simulate this, I get "z" for all three outputs...And I have no idea why!

Can anyone help me, please? How can I get rid of these "z"s? What's wrong?! O.O

I would appreciate your help in advance!!

=)