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Did i do this right? VHDL wave form

  1. Oct 20, 2006 #1
    Hello everyone.

    We just started VHDL using ModelSim and I want to make sure i did this right. The assignment was to:
    Modify the Input Sequence. Once you complete the simulation with the given VHDL files, you are requred to moidfy the file "testadder.vhd" to simulate the full adder using the gray code input sequence.


    a,b,cin: 000 -> 001 -> 011 -> 010 -> 110 -> 111 -> 101 -> 100 -> 000


    Assume for each input signal, a transition (from 0 to 1 or from 1 to 0) is only allowed after at least 10 nanoseconds from the previous transition.

    here is the code I modified:
    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity testadder is
    end testadder;

    architecture testbench of testadder is
    signal a,b,ci,s,co:std_logic;

    component fulladder
    port(
       a:in std_logic;
       b:in std_logic;
       ci:in std_logic;
       co:out std_logic;
       s:out std_logic);
    end component;

    begin
    add:    fulladder PORT MAP(a=>a,b=>b,ci=>ci,s=>s,co=>co);
        a<='0','1' after 40 ns, '0' after 80ns;
        b<='0','1' after 20 ns, '0' after 60ns;
        ci<='0','1' after 10 ns, '0' after 30ns, '1' after 50ns, '0' after 70ns;
    end testbench;
    and here is the wave form:
    [​IMG]
     
  2. jcsd
  3. Oct 20, 2006 #2

    berkeman

    User Avatar

    Staff: Mentor

    Sorry, I'm not tracking. You are adding a+b+c and getting the 2-bit sum what?
     
  4. Oct 20, 2006 #3
    I guess its a full adder.... but she didnt want us to mess around with the full adder code, she just wanted us to change the input values of the full adder.

    Here is all the code:
    this is the add.vhd
    Code (Text):

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity fulladder is
    Port(
       a:in std_logic;
       b:in std_logic;
       ci:in std_logic;
       s:out std_logic;
       co:out std_logic);
    end fulladder;

    architecture behavior of fulladder is
    begin
        s <= a xor b xor ci;
        co <= (a and b) or (a and ci) or (b and ci);
    end behavior;
     
    Here is the test values the adder is getting:
    Code (Text):

    use IEEE.STD_LOGIC_1164.ALL;

    entity testadder is
    end testadder;

    architecture testbench of testadder is
    signal a,b,ci,s,co:std_logic;

    component fulladder
    port(
       a:in std_logic;
       b:in std_logic;
       ci:in std_logic;
       co:out std_logic;
       s:out std_logic);
    end component;

    begin
    add:    fulladder PORT MAP(a=>a,b=>b,ci=>ci,s=>s,co=>co);
        a<='0','1' after 40 ns, '0' after 80ns;
        b<='0','1' after 20 ns, '0' after 60ns;
        ci<='0','1' after 10 ns, '0' after 30ns, '1' after 50ns, '0' after 70ns;
    end testbench;
     
    The directions where:
    Modify the Input Sequence. Once you complete the simulation with the given VHDL files, you are requred to moidfy the file "testadder.vhd" to simulate the full adder using the gray code input sequence.


    a,b,cin: 000 -> 001 -> 011 -> 010 -> 110 -> 111 -> 101 -> 100 -> 000


    Assume for each input signal, a transition (from 0 to 1 or from 1 to 0) is only allowed after at least 10 nanoseconds from the previous transition.



    I'm still very new and not sure what alot of this means...but yes there are
    Code (Text):

     a:in std_logic;
       b:in std_logic;
       ci:in std_logic;
       co:out std_logic;
       s:out std_logic);
     
    3 input values, a, b, anc ci, and 2 output values, co and s
     
    Last edited: Oct 20, 2006
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