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We just started VHDL using ModelSim and I want to make sure i did this right. The assignment was to:

Modify the Input Sequence. Once you complete the simulation with the given VHDL files, you are requred to moidfy the file "testadder.vhd" to simulate the full adder using the gray code input sequence.

a,b,cin: 000 -> 001 -> 011 -> 010 -> 110 -> 111 -> 101 -> 100 -> 000

Assume for each input signal, a transition (from 0 to 1 or from 1 to 0) is only allowed after at least 10 nanoseconds from the previous transition.

here is the code I modified:

and here is the wave form:Code (Text):library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity testadder is

end testadder;

architecture testbench of testadder is

signal a,b,ci,s,co:std_logic;

component fulladder

port(

a:in std_logic;

b:in std_logic;

ci:in std_logic;

co:out std_logic;

s:out std_logic);

end component;

begin

add: fulladder PORT MAP(a=>a,b=>b,ci=>ci,s=>s,co=>co);

a<='0','1' after 40 ns, '0' after 80ns;

b<='0','1' after 20 ns, '0' after 60ns;

ci<='0','1' after 10 ns, '0' after 30ns, '1' after 50ns, '0' after 70ns;

end testbench;

http://suprfile.com/src/1/3ul55mx/CorySanchezWave.gif [Broken]

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# Did i do this right? VHDL wave form

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