PS Here is one way to build the state machine in your problem..
Two D-Type latches are used to hold the state bits. A very small Read Only Memory (ROM) is used to implement the truth table. Q0, Q1 and X are used as address bits to the ROM. The ROM data outputs D0, D1, D2 are used to generate the "next state" Q0+ and Q1+ and the output Z.
You don't have to use a ROM to implement this. You could work out how to generate (for example) Q0+ from Q1,Q0 an X using logic gates instead.
One thing missing from my circuit is a reset pin. Typically this would reset both latches to 00 (or some other known state) when power is first applied.