Digital Logic State Diagram

  1. Hi, I am designing a system to run a certain sequence when the control input is off, and then run a different sequence when the control input is on. When drawing a state diagram, for the loop where the control input is on, can the system repeat the same state twice throughout its sequence and therefore miss one of the other states out??

    E.g.

    Control = 0: 0000, 0001, 0010, 0011, 0100, 0101 etc.

    Control = 1: 0000, 0100, 0010, 0011, 0010, 0101 etc (I.e. State 0001 is not used but 0010 used twice)
     
  2. jcsd
  3. Since control=0 is just a counter it might be easier to mux two state machines and mux them with Control as the muxing variable.

    Otherwise it's going to be a bit tricky and you will need some additional state variables (besides your state vector output).
     
  4. You cannot use a state twice without something that makes the two occurences unique, essentially making another state.

    If I'm in state 0010, I need to somehow know whether to go to 0011 or 0101.

    The easiest way to do this is dependent of the nature of the output signals you are driving. Do they need to be glitch free (meaning no decoded control signals) or ?.

    Sometimes a state machine is followed by (or contains additional) flops to produce glitch-free outputs, and sometimes that is all encoded into the state flops.

    I generally write my state machines in verilog and do it the way that makes it most easily followed. I never encode outputs into state flops. I always have state numbers be just that --- state numbers ---- not control signals.
     
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