Double negation in logic circuit

[Baroness]

Probably a very simple answer here...

I'm creating a logic circuit using only NAND gates. I have 4 inputs, A B C and D, but I am just using a single 'path'/part of the equation for this question, that being A'B = F, F being the output.

Full equation...

AB'C + AB'D' + A'B + A'C = F
F has a NAND gate directly before it, negating any 'paths' leading into F
I'm just using this highlighted part of the equation as an example

Solutions...

I have two ideas, I just want to know if one is more appropriate or correct than the other.

a)
Firstly, split A and feed through NAND gate, giving A'
Run A' and B through NAND gate to combine into A"B'
PROBLEM: The input of that path to F needs to be A'B, so A"B' will need to be split and passed through a NAND gate to give the correct input into the final gate, so...
Split A"B' and pass through NAND gate, giving A"'B" (DeMorgans cancels to A'B - correct?)
By my thinking, that should work, but it has a lot of split>NAND gate situations in there.

b)
Split B and feed through NAND gate, giving B'
Run A and B' through NAND gate, giving A'B"
PROBLEM: This is where I get muddled...
Because there's a single negation on A and a double on B, my mind is saying that I can cancel off the one's on B, leaving only A negated, giving the A'B I need BUT...
Canceling that double negation over B would be considered 'breaking the bar' in DeMorgans, and require me to change the sign between A and B, giving a completely different equation (say A' + B, right?).

So I have a very strong feeling that a) is the option to go for. Is my thinking right?

 

[Valkarie]

Yes, your thinking is correct. The first solution (a) is the most appropriate way to solve this problem. By splitting A and passing it through a NAND gate, you create A', which can then be combined with B using another NAND gate to create A'B. This is the correct input for the final gate. You cannot use De Morgan's Law to cancel out the double negation over B without changing the equation, so solution (b) would not work.

 

[Mene]

I would suggest that option a) is the correct approach in this scenario. While option b) may seem simpler, it involves breaking the bar in DeMorgan's law which can lead to incorrect results. Option a) follows the correct order of operations and ensures that the inputs are correctly negated before being combined into the final output. It may involve more steps, but it ensures accuracy and avoids any potential errors. Additionally, using the DeMorgan's law to cancel out the double negation in option b) may not always be applicable in other logic circuits, making option a) a more generalizable solution.