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Dynamic array in Verilog

  1. Jul 22, 2012 #1
    hello everyone
    I know that dynamic array is not supported in Verilog and Quartus. I want to know does anybody has an idea or algorithm to use instead of dynamic array. I mean I am searching for something that works instead of a dynamic array.
    thanks
     
  2. jcsd
  3. Jul 22, 2012 #2
    nadersb,
    Dynamic arrays is a verification feature, i.e. for use in test bench. It is not generally synthesizable.

    Think of what Quartus would have to do to synthesize int dyn_array[];. How much memory, or how many logic elements should it assign? How would it know if the logic fit in a the target device?

    Perhaps explain why you think you need a synthesizable dynamic array.
     
    Last edited: Jul 22, 2012
  4. Jul 23, 2012 #3
    yes I know it is not synthesizable because the problems you have mentioned and thats why I need something else.
    let me explain more, I have a module that its input is not fixed size. it can be 16,32,64... bits. the easiest solution is to use a large enough array for input, but it wastes too much logic cells. so I am thinking and searching for an algorithm that help me in this case.
     
  5. Jul 23, 2012 #4
    When is the size determined, during instantiation of the module or after download?
     
  6. Jul 23, 2012 #5
    size itself is an input. it is a filter that number of its coefficient is changeable.and size depends on how accurate filter should be.
     
  7. Jul 23, 2012 #6
    Is it an input to the module during instantiation or an input to the FPGA itself (say from software) after it has been downloaded?
     
  8. Jul 23, 2012 #7
    it is an input to FPGA itself
     
  9. Jul 24, 2012 #8
    Sounds like your options are either dynamic reconfiguration, or design to accomodate the largest possible size.

    If this is a transversal (FIR) filter of max length, say, 128 coefficients than you need enough RAM to store these coefficients anyway. If you want to scale back the accuracy then just zero out the unused coefficients. Filter will work normally except with some non-optimal delay.

    Of course I am speculating without having any idea about your architecture.
     
  10. Jul 24, 2012 #9
    yes I think so. I think there is no way instead of using large size array unfortunately
     
  11. Jul 24, 2012 #10

    jim hardy

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    hmmm

    are string variables dimensionable on the fly?

    ignore suggestion if it's silly - i'm still living in the age of interpreted Basic.


    old jim
     
  12. Jul 25, 2012 #11
    Hey Jim,

    In an ordinary programming language the programmer often has the luxury of assuming that there is limitless memory available. When the program is run and it decides it needs a certain amount of memory, say for a string variable, it makes the request to the operating system. The operating system keeps track of how much memory is available, and who is using what, and will allocate a block to this program. Later, the program can notify the operating system that it no longer needs this memory, and it gets returned to "the heap".

    Synthesizable Verilog kind of looks like a programming language but is actually a "hardware description language". It is really just a text way of doing what we did years ago with pencil, stencil, and D-size schematic sheet to design digital logic. If I needed a register big enough to hold a 32-bit word, I drew in 32 flip-flops on my schematic, then build my board. Today in verilog we "instantiate a 32 bit register" and program the FPGA. In both cases a piece of hardware has been created. And, just like there was limited real estate on my digital logic board, there are limited logic resources available within an FPGA, so we try to be very conservative (the point of the OPs post). If I change my mind and decide I needed it to be a 64-bit register, I have to change the verilog code, and reprogram the FPGA and hope that it can "fit" the design. If it needs to be 32-bit most of the time, and 64-bit occasionally, I need to build it with 64-bits.

    Of course, this is somewhat simplified for clarity's sake. It is actually pretty unlikely that bumping a single register up in size by 32 bits would cause a fitting issue. Even modest FPGAs today provide tens of thousands of flip-flops.
     
    Last edited: Jul 25, 2012
  13. Jul 25, 2012 #12

    jim hardy

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    Thanks EMIguy for that neat introduction. What amazing tools you have these days!

    i remember an old Honeywell DDP15 with discrete transistor flip-flops and drum memory about a foot diameter
    it replaced the old 12AU7 based machine for an airline reservation system....
    but in my heyday we had 4 bit MSI registers...

    anyhow , thanks again. I'll probably never use such a thing but it is comforting to have a rudimentary idea of its existence.

    old jim
     
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