Dynamic RAM memory cells

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Summary
Some questions about dynamic RAM memory cells such as refresh cycle, cost per bit, etc.
Hi,

Could you please help me with the questions below? All of the questions are related to each other. Thank you.

Question 1:
Please have a look on this attachment. The following text is from the parts highlighted in yellow in attachment.

"Dynamic memory cells store a data bit in a small capacitor rather than in a latch. The advantage of this type of cell is that it is very simple, thus allowing very large memory arrays to be constructed on a chip at a lower cost per bit. The disadvantage is that the storage capacitor cannot hold its charge over an extended period of time and will lose the stored data bit unless its charge is refreshed periodically. To refresh requires additional memory circuitry and complicates the operation of the DRAM."

"
Again, because charge stored in a capacitor will leak off, the DRAM cell requires a frequent refresh operation to preserve the stored data bit. This requirement results in more complex circuitry than in a SRAM."

Some of the text from the same passage seems self-contradictory but I'd say that the author is trying to say that advantages of using DRAM over-weighs its disadvantages, and at the end of day its per bit price is still less than that of SRAM. Do I have it correct?

Question 2:
In my opinion FIGURE 11-18 under Address Multiplexing section is misleading. Let me elaborate. The text in the para right under FIGURE 11-18 says, "First, the 10-bit row address is latched into the row address register. Next, the 10-bit column address is latched into the column address register. The row address and the column address are decoded to select one of the 1,048,576 addresses (220 = 1,048,576) in the memory array". The shown Row line, which activates the gate, is fine but the bit line or Column line is quite misleading or incorrect, in my humble opinion. I have tried to fix it in this attachment. The 'yellow' and 'green' buffers could be active-HIGH or active-LOW depending upon the output of address decoders; as shown the buffers are active-HIGH. Each Row line has an input which is turned on by the address decoder and each column line also has an input buffer which is controlled by column address decoder, and together they are used to select a single cell in the memory array. Do I make sense?

Question 3:
In the very last two paragraphs in green the following is said.

"The two types of refresh operations are RAS' only refresh and CAS' before RAS' refresh. RAS'-only refresh consists of a RAS' transition to the LOW (active) state, which latches the address of the row to be refreshed while CAS' remains HIGH (inactive) throughout the cycle. An external counter is used to provide the row addresses for this type of operation.

The CAS' before RAS' refresh is initiated by CAS' going LOW before RAS' goes LOW. This sequence activates an internal refresh counter that generates the row address to be refreshed. This address is switched by the data selector into the row decoder."

(The apostrophe means bar over the word.)

You might find FIGURE 11-19 helpful. I don't understand refresh operation could be carried for "RAS'-only refresh" when CAS' remains HIGH (inactive) throughout the cycle. An external counter lets you to switch from one row to another and I understand that each row line connects to the gates of all transistors in that row. How could you refresh the charge when none of the columns have been selected?

I'm also confused about "CAS' before RAS' refresh". I understand that first CAS, i.e. Column Address Select, goes LOW and then RAS, i.e. Row Address Select, goes LOW. To switch rows, an internal refresh counter is used but what about the columns? How do you switch from one column to another? Don't you need a counter too?

Question 4:
This question is directly related to Question 3.

The following text could be found in this PDF under the section BURST REFRESH on page #1 : https://downloads.reactivemicro.com/Electronics/DRAM/DRAM Refresh.pdf . (BTW, you could access the same PDF here from my Google drive where I have highlighted the text.)

"BURST REFRESH
Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh other commands are not allowed. Below is a drawing representing burst and distributed refresh.

For example: a 4 Meg x 1 requires 1,024 consecutive refresh cycles, each of which will use 130ns (tRC) for a 70ns device:
1,024 cycles * 130ns = 133,120ns = 0.133ms
16ms - 0.133ms = 15.867ms


Approximately 0.13ms would be spent performing refresh, and the remaining 15.87ms could be spent reading and writing; then burst refresh would occur again, and so on."

Where does this "for a 70 ns device" come from? What does this "70 ns" time represent?

Thanks a lot for your time and help!
 

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berkeman

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Some of the text from the same passage seems self-contradictory but I'd say that the author is trying to say that advantages of using DRAM over-weighs its disadvantages, and at the end of day its per bit price is still less than that of SRAM. Do I have it correct?
I'll help with Question #1 for now. Yes, you do have it correct. It's confusing as stated because they should have said that the control circuitry is more complicated, but the memory cells themselves are simpler and smaller. And since the bulk of the memory IC area is taken up with the storage cells (and not so much by the control circuitry), that is why overall DRAM has a cost advantage.
 
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Thank you!

I'll take the easy/short one here. :oldbiggrin:

It's the Read Access Time of the memory chip.
See: https://www.webopedia.com/TERM/A/access_time.html
Or: https://www.google.com/search?&q=dram+memory+access+time

Cheers,
Tom
But I forgot to ask about the "16 ms" figure. Where does it come from? :)

For example: a 4 Meg x 1 requires 1,024 consecutive refresh cycles, each of which will use 130ns (tRC) for a 70ns device:
1,024 cycles * 130ns = 133,120ns = 0.133ms
16ms - 0.133ms = 15.867ms
 

berkeman

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But I forgot to ask about the "16 ms" figure. Where does it come from? :)
Where do YOU think it comes from? :smile:
 

berkeman

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LOL. But what does that time mean? What is it a measure of?
It's the Refresh Time and all the cells of DRAM must be refreshed during that time frame otherwise data might get lost. I hope I have it correct. Thanks.
 

berkeman

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It's the Refresh Time and all the cells of DRAM must be refreshed during that time frame otherwise data might get lost. I hope I have it correct. Thanks.
Correct, And can you see one other subtle issue with DRAM memory related to the parallel processes of normal CPU memory accesses and refresh? What happens when the CPU needs to fetch from DRAM during a refresh cycle of that same location?
 
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Correct, And can you see one other subtle issue with DRAM memory related to the parallel processes of normal CPU memory accesses and refresh? What happens when the CPU needs to fetch from DRAM during a refresh cycle of that same location?
In both Burst Refresh and Distributed Refresh Modes data access is suspended for the CPU. Though, in Distributed Mode, individual refresh cycles are spread over entire range of Refresh Time so that CPU could be given access in between those refresh cycles. Is this what you were referring to?
 

phyzguy

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If I could weigh in on a couple of these things:

The shown Row line, which activates the gate, is fine but the bit line or Column line is quite misleading or incorrect, in my humble opinion. I have tried to fix it in this attachment. The 'yellow' and 'green' buffers could be active-HIGH or active-LOW depending upon the output of address decoders; as shown the buffers are active-HIGH. Each Row line has an input which is turned on by the address decoder and each column line also has an input buffer which is controlled by column address decoder, and together they are used to select a single cell in the memory array. Do I make sense?
Your "fixed up" drawing can't work. A buffer like the column address buffer you have in green only flows in one direction. There is no way for the data to travel backwards through your buffer from the bit line to the sense amplifier.

... An external counter lets you to switch from one row to another and I understand that each row line connects to the gates of all transistors in that row. How could you refresh the charge when none of the columns have been selected?

I'm also confused about "CAS' before RAS' refresh". I understand that first CAS, i.e. Column Address Select, goes LOW and then RAS, i.e. Row Address Select, goes LOW. To switch rows, an internal refresh counter is used but what about the columns? How do you switch from one column to another? Don't you need a counter too?
You need to study how the latching style sense amplifiers in modern DRAMs work. Each column has its own latching style sense amplifier. When you select a row and enable all of the sense amplifiers, all of the bit lines will be driven high or low (depending on the data stored in the cell on that row). This refreshes the data in the DRAM cells on all columns simultaneously. There is no need to select a column and drive data out to the output buffers.
 
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Thank you!

Your "fixed up" drawing can't work. A buffer like the column address buffer you have in green only flows in one direction. There is no way for the data to travel backwards through your buffer from the bit line to the sense amplifier.
You are correct. Thanks for pointing this out.

You need to study how the latching style sense amplifiers in modern DRAMs work. Each column has its own latching style sense amplifier. When you select a row and enable all of the sense amplifiers, all of the bit lines will be driven high or low (depending on the data stored in the cell on that row). This refreshes the data in the DRAM cells on all columns simultaneously. There is no need to select a column and drive data out to the output buffers.
I'm only trying to understand the basic design of DRAM. Understanding such stuff in detail is really difficult especially when technology changes and improves on almost daily basis.

In this attachment, "sense_amplifier1", only one buffer is called a sense amplifier or output buffer but I don't think you were referring to just one buffer.

Please have a look on this attachment, "dram_cell1". In my opinion, each column line connects to column address decoder, and each column line needs to have its own input column address buffer (green), output column address buffer (blue), output buffer/sense amplifier, and refresh buffer. Perhaps, this is what you were saying. Please let me know if I have it correct.
 

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phyzguy

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Well, you're trying to understand the DRAM architecture at a high level, but then you're asking detailed questions like, "how come I don't have to enable the column address buffers during a refresh?" You can't have it both ways. You're never going to get the detailed understanding of how it all works that you're searching for without studying the circuits in detail. To get the understanding you want, you're going to have to go down to the transistor level. Have you tried this wiki article? It's a pretty good start. The figure "Basic structure of a DRAM cell array" shows the primary sense amplifier, which latches the data during a read. Note that because of this latching function, any time the cell is accessed, it is automatically refreshed. In fact, it must be refreshed whenever it is read, because the act of reading drains off the stored charge in the capacitor.

By the way, no, your post #12 is not correct. You won't be able to understand it at the logic gate level. You have to drill down to the transistor level. Another approach is to just accept a high level description, like: "you select a row, select a column, and the data stored in the memory cell at the intersection of the row and column gets read out". Voila! simple!
 
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Thank you!

Please have a look on this attachment. The attachment is divided into three parts.

This text tries to explain it better. In Part 2 it says, "Because the cross-coupled latch is highly sensitive, it remains connected across two bitlines in order to balance the capacitive load on the two nodes of the latch and to share the sense amplifier between two columns of cells". Please have a look on this attachment showing the figure "Basic structure of a DRAM cell array" from the mentioned Wikipedia article, https://en.wikipedia.org/wiki/Dynamic_random-access_memory . You can see that on the same row transistors are connected in alternate fashion which shows how a cross-coupled latch or sense amplifier is connected across two bitlines.

Figure 8.25 from Part 2 assumes that the stored value is 1 or HIGH. First precharge is performed to Vdd/2 and voltage on both bitlines equalizes, then wordline is raised to high voltage, and data is read. We can see that as the time progresses voltage keeps rising on BL but on BL' falls toward 0 V, and the storage node voltage also rises back to its original value because wordline remains HIGH. Part 1 explains how read and write operations are performed.

I think that I was reading too much into the original text which was only trying to convey the basic operation of the circuit. But at the same time, if my attempt, "dram_cell1", is not correct, then, in my humble opinion, the author of original text is also not being precise. This is the original text. He could have done a better job with FIGURE 11-18 and in the very last two paragraphs in green at the end where he briefly mentioned the two types of refresh operations are RAS' only refresh and CAS' before RAS' refresh.

Thanks a lot for your help!
 

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phyzguy

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Your first attachment (with the three parts) in post # 14 is pretty good. I agree that what you called the "original text" is misleading. Sometimes the people that write these summaries don't really understand how they work. It's good that you keep questioning and keep trying to understand how these things work!
 

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