Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

FET switch

  1. Jul 31, 2009 #1
    Hello. I need some help. I've realized a circuit in which I sample extremely low currents (<100 pA) using charge transfer to a 3.3pF cap, through a low leak FET (2N4117 reverse gate current about 1 pA). The problem : Instead of progressively charging the cap, this one seems to be charged and discharged during the same pulse sent to the gate.

    Technical data : gate pulse from -4 V (rest level) to 0 V during 400 ns (Fet switched On) , each 50 µs. Where is the error ? You will find here enclosed a very simplified schema.

    Attached Files:

  2. jcsd
  3. Jul 31, 2009 #2
    Your 10 pA current source should be changed to a voltage source plus a very hi-meg resistor (like 10^10 ohms), so the current will stop charging the cap when the FET is off.
  4. Jul 31, 2009 #3
    Thanks for yr answer. Unfortunately, my input is a very low current coming from a physics device. I'm affraid, if I introduce a large resistor to convert current in voltage, to also introduce undesirable noise which will produce a very bad s/n.
  5. Jul 31, 2009 #4
    My comment was only with the schematic; nothing else. The current source in SPICE is a constant current source, and will go to 1 megavolt if necessary to maintain a constant current during the FET OFF, so you will not be able to gate the current source with a FET in SPICE.
    Many years ago I built some circuits with about a 10 pF integrating capacitor in the feedback loop of an op-amp with femptoamp leakage current. The circuit was a straight integrator followed by a one-shot which used the 1N4117 FET to inject a specific amount of charge (a few picocoulombs) back into the op-amp input. The charge injection was tricky because the gate-to-source and gate-to-drain capacitance injected a signal which had to be compensated. There was a resistor between the FET and summing junction to limit the charge transfer per feedback pulse. The digital pulses from the one-shot were digitally integrated in a decade counter.
    Is there any way you can balance out the dark current (How much is it?) from your physics device (What is it?), so your difference signal is the the signal current from your physics device. How long are your data collection runs? Your net signal is about 1 picoamp (100 pA x ,0.4/50), so if your runs were say 10 minutes, the collected charge would be 600 picocoulombs.
  6. Aug 1, 2009 #5
    Your reply is of very high interest. Do you have any schematics of the device you realized in the past, it will be very helpful for my project. In a few word, I'm an amateur scientist who has made a comprehensive Time of flight Mass Spectrometer. Input current is provided by the contact of accelerated ions on a Faraday cap. This explains why phenomenon is almost periodic and quickly variable. As it was difficult to get wide band and low current (transimpedance amplifier) my idea was to sample the input current, and I've realized the boards, remote controlled by a µcontroller and a PC ... My very last, but not the least problem, is sampling !
  7. Aug 1, 2009 #6
    The best source for an up-to-date schematic is available from either John larson (jal@fnal.gov) or Fred Krueger (fkrueger@fnal.gov) at Fermilab (FNAL). Here is a recent paper (pay per view):
    Is it possible to zero out the signal current when the beam is off? How long are your data runs (the 50 usec data collection runs)? Is it 1 second, or 5 minutes? How much charge (Coulombs) do you expect every 400 nsec pulse? How much charge (Coulombs) do you expect for each data run? Why do you need to gate off after every 400 nsec pulse?
    [Added questions] What is the shunt capacitance of the Faraday cup and how long is the cable (what is shunt capcitance) from the cup to your electronics? You are integrating the signal on this shunt capacitance. Your background (beam off) leakage current should be very small. How big is it?
    Last edited: Aug 1, 2009
  8. Aug 2, 2009 #7
    Well. Faraday cup capacitance is 20 pF, cable length is 50 cm ... Sampling uses a window of 400 ns ( for example ) which is moved at the end of every integrating cycle which longs about 3s. To better explain my chalenge, imagine a scope on which you observe a periodic signal in which higher frequency is for instance 5 MHz, but ... input of this scope instead to be a variable voltage is a variable very low current generally less than 100 pA. I've previously developped a traditionnal transimpedance amplifier but unfortunately parasic capacitance (mainly parallel to the 1 GOhm resistor ) made the bandwidth around 5 or 10 kHz, very far from 5 MHz. That is the reason for which I imagined to start on a sampling system. PS : as my electrometer is remote controlled with a µcontroller and a PC, I've no problem to make statistics and to determine the 'dark' current.
  9. Aug 2, 2009 #8
    I am not quite sure what you are doing, and why you need all the gating. I do understand that your signal from the Faraday cup is about 100 pA. Is this peak or average current during 1 second? How many picoCoulombs of signal from the Faraday cup do you collect in 1 second? 100 pC? How much signal does the noise contribute during this period? If the noise is >= 10 pA, where does it come from? Why can't you zero your integrator before the run and measure the intergrator output at the end of the run?
  10. Aug 3, 2009 #9
    Sorry I'm unlucky in my explanations. Have a look to the attached picture. Lets assume that highest peak represents a 100 pA Faraday cup current, and that time width is 50 µs. By traditionnal transimpedance amplifier bandwidth is not wide enought to visualise it and so I use a sampling system.

    1) Cap is discharged.
    2 ) During, lets say 3 s, every 40 µs (relative position of the peak) after the beginning of a 50 µs cycle I sample the input current for 400 ns.
    3 ) At the end of the 3 s run, sampling is stopped, cap voltage is digitalized, cap is then discharged, and cycle restart with an other window, lets say 41 µs in respect to the beginning pg the 50 µs time base.

    It's works (almost) except that using a 2N4117 (probably in a wrong way), during sampling window, cap is charged, and discharged (leak by the gate ?) . That's my problem. Ideally CD4066 will be wonderful for my project, except that its "Off" leak is not acceptable with the currents I work with.

    Attached Files:

  11. Aug 3, 2009 #10
    I still do not understand why you do not just open the integrator gate and integrate your signal for 3 seconds. Your Faraday cup signal is dc charge, so unless you have leakage current (like dark current) someplace, you should have a clean signal w/o gating during the 3 second integration time. What is your time-average Faraday cup signal for the 3 second run- 300 picoCoulombs?
  12. Aug 3, 2009 #11
    Because input signal is absolutely variable during 50 µs, and périodic with T=50 µs. It's like a digital scope but with current instead of voltage as input.
  13. Aug 3, 2009 #12
    You are collecting charge, not an AC signal, in your Faraday cup. Suppose you collect charge Q during 3 seconds. Suppose your background charge signal would be zero during the same period. So the collected charge would be Q whether or not you gate the signal for 400 nsec every 50 usec. So don't gate the signal every 50 usec.
  14. Aug 5, 2009 #13
    Mike Here. I've seen the exact same problem you're dealing with - a mass spec with a tiny charge coming back.
    Firstly, the mass spec had a gating grid to shut off the incoming particles during except for the time in which you sampled.
    Next, the the resulting signal had to be processed close to the cup. Run it through a cable and the tribolectric noise will be an issue. In this case, the signal was conditioned by an integrator which was mounted in the vacuum.
    Finally, the integrator was a major peice of work. It had a JFET input amp with a glass capacitor for the feedback and an external reed relay that did the reset. Ah, the glory of yesteryear....
    If I were you, I'd look into the Burr-Brown/Ti ACF2101 sample and hold / integrator. Working off-die, you won't get less charge injection with a semiconductor device. Mount it right off your seal, reset and start it integrating before your peak is expected.
    As for wanting to look at a particular portion of the wave, I'd use two sample and holds. One to grab the value from the integrator before and then another for immeadiately after the event. Take the difference of those sample holds, and either grab it quick with a long time constant sample hold, or catch it with a fast A/D. Be sure to make a dry run before each trial. That will give you a baseline to subtract the offsets and charge injection.
    With 18-20 bits readily available, most folks just leave the A/D streaming the output of the integrator, and get the transition using math.
    . Best Wishes and Good Luck, I wish you well with your experiments,
    . - Mike
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Similar Discussions: FET switch
  1. Double FET (Replies: 5)