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Find latency and throughput for the electronic system

  1. Feb 13, 2012 #1
    ---a(x) ----[FIFO]----a(x)------>
    [SOURCE]-----a(xy)---> { } ----a(x).b---> [SINK]

    In this system above, the source can generate one piece of data axy per clock cycle. A portion of this data ax goes straight into a FIFO. If the FIFO is full, the source is prevented from generating any data.

    The rest of the data ay is used as an address to fetch data from the module EXT. For each request ay sent to EXT, a sequence of n words b1..n are returned. These are returned serially at the rate of one word per clock cycle with the first word b1 appearing d clock cycles after the original request was made. The EXT module is perfectly pipelined and can queue up an infinite amount of requests.

    The sequence b1..n is put through a serial to parallel converter (not shown) to create a single piece of data b which is combined with one piece of data out of the FIFO to create axb.

    The sink can accept one piece of data axb per clock cycle, but it cannot accept a word ax without a corresponding word b.

    All interfaces in the system have flow control so need not run at maximum rate.

    • What is the latency through the system?
    • What is the maximum throughput of this system?
    • What is the minimum size that the FIFO can be to achieve this maximum throughput?
    • Draw a waveform diagram for the system above where n=2 and d=6 showing the output of the source, FIFO and EXT and the input to the sink.

    Attached Files:

  2. jcsd
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