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Finite state machine problem

  1. Apr 8, 2010 #1
    1. The problem statement, all variables and given/known data

    2. Relevant equations

    There aren't really any relevant equations.

    3. The attempt at a solution

    Ok so I just want to see if my idea for the state diagram seems ok, I'm going to give it in table form here but its the same info.

    Code (Text):
    F  |  Bk  |  A  |  B  |  C  |  D  
    0  |  0  |  A   |  B  |  C  |  D
    0  |  1  |  D   |  A  |  A  |  D
    1  |  0  |  B   |  C  |  C  |  A
    The F is the forward button, the Bk the back button. A is the stop state, B is the forward state 1, C is the forward state 2, D is the backward state. I then put this into a state diagram with the 3 possible changes/inputs for each state. However should I have included the clock and the reset button in this? So that there would be 16 possible inputs?

    P.S. I am not concerned about the VHDL problem at the moment although I may ask for help with it at another date.
  2. jcsd
  3. Apr 8, 2010 #2


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    Your table looks fine, though including the reset wouldn't be a bad idea. The clock, however, simply tells the state machine when to advance to the next state; it's not an input for determining what the next state is.
  4. Apr 8, 2010 #3
    Hmm ok, it was just the part in the question about holding down the buttons for more than one clock cycle that threw me. I guess that part may only be relevant when it comes to writing the VHDL.

    I'm going to assume that the reset button sets everything to zero, and therefore the stop state. Ok thanks for your input, I'll post here again with my code to see if its ok.
  5. Apr 8, 2010 #4


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    I just realized there is a problem with your state machine, and it has to do with a button push lasting for more than one clock cycle. When you make a transition into the gear-I state, you don't want to leave it before the button has been released and pressed again, otherwise you'll just fly right through that state with a single button press if the clock cycle is short, as it very likely is.
  6. Apr 9, 2010 #5
    Ahh very true, hmm how could I get around that then. I know how I could do it in the VHDL code
    Code (Text):
    if ((clock = '1' and clock'event) and (SFW = '1' and SFW'event)) then
    state <= stateB;
    end if;
    Or something along those lines at least, but I'm unsure how I'd represent that in a state table? Could I just present the state table as is and say that state transitions can only occur at a push button event and it being equal to one?

    So I've just read up on this a bit more and realised that a process generally can only have one edge sensitve input, therefore the code should be different.
    Code (Text):
    seq:process(clock) is
    if (clock = '1' and clock'event) then
    present_state <= next_state;
    end if;
    end process seq;

    com: process (SFW, SBW, reset_N);
    CASE when A =>
       forwardgear1= '0';
          if (SFW = '1' and SFW'event) then
          next_state <= B;
          elsif (SBW = '1' and SBW'event) then
          next_state <= D;
          else next_state <= A;
          end if;

    when B=> ........etc
    Hmm I thought I had worked it out there but realised the second process would still have more than one edge sensitive statement.
    Last edited: Apr 9, 2010
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