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Flip flops

  1. Jan 18, 2006 #1
    Can someone please check to see if I drew teh circuit right? It's supposed to be 3 D flip-flops wired together such that D1 = Q3, etc. on the bottom. And how would I go about drawing the timing diagrams for the outputs if all of them start in the set state. I get really confused about timng diagrams. I understand the basics for the other types of flip flops if there is only one but when there are multiple ones with gates attached, I don't know what to do. Any suggestions for really good websites or can someone explain it? Thank you!
     

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    Last edited: Jan 18, 2006
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  3. Jan 18, 2006 #2

    berkeman

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    Staff: Mentor

    The circuit is drawn wrong. It shows the output of the XOR gate driving the output Q3 of the third FF.

    After you redraw the circuit, you can draw the timing diagram by first drawing a 50% duty cycle clock waveform across a page of grid paper or engineering paper. At each rising edge of the clock (as the FFs are drawn), the D inputs will clock through to the Q outputs of each FF. So draw the intial D input values coming in from the left of the timing diagram, then at the first rising clock edge, carry the D inputs through to the appropriage Q outputs. Then figure out what that does to the next D input values, and show those on your diagram. Then at the 2nd clock rising edge, show those D inputs clocking through to change the appropriate Q outputs, etc.

    Make sense?
     
  4. Jan 19, 2006 #3
    thanks berkeman. yes i think that makes sense but what should i assume the first input D1 is, 1 or 0? it just says to assume all the set states in all the circuits is Q=1 but for D flip-flops, if Q=1, D could be either 0 or 1 right because the only thing that matters is what Qnext is? should the XOR gate even be there at all or i don't know how to go about making the last equality true, that Q1 XOR Q3.
     
  5. Jan 19, 2006 #4

    berkeman

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    Staff: Mentor

    As for the XOR, it should be drawn as a 2-input XOR gate, with its two inputs as Q1 and Q3, and its output going to D2. That's the equation in the drawing, anyway.

    As for the initial state of the state machine, that is up to you or should be specified in the problem statement. The flops aren't shown with a reset input, but they really should be. Any real-world state machine has to have a reset state to start things off. Since there are 3 FFs, this state machine has 8 potential states. Usually you would start off the state machine in the reset state Q[3:1] = 0b000, and at each clock tick, the machine would transition to the next state. If your FFs started off at 0b000, then given the equations, the next state would be 0b010. Do you see why?

    The best thing to do is to draw the state diagram for this machine, and trace out the path that it will take, assuming it starts in the reset state. It may be that all 8 states are not visited, given the starting state of 0b000. The timing diagram will just show the D and Q values of the circuit, as it transitions from state to state.

    BTW, in the real world when you design a state machine, you will also be careful to make sure that any unused states (those that you don't get to through a natural progression from the reset state) have their own unconditional transitions back to some legal state, usually the reset state.
     
  6. Jan 20, 2006 #5
    Hi Berkeman and thank you for replying. I still don't get it. I understand how to draw the circuit now but I don't get how it works. Is it possible for you to walk me through it step by step or start explaining from the beginning? I don't understand the notations you used. Is b begin? Thank you so much!
     
  7. Jan 21, 2006 #6

    berkeman

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    No, sorry bud. I was using standard notation for binary. In C or many CPLD/FPGA compilers, the standard notation is:

    0x -- hex
    0b -- binary

    etc.

    Is that enough to explain it all?
     
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