Homework Help: Forward Transfer Characteristic of Triode - Gray Searle P1.1

Tags:
1. Jan 2, 2018

TRAyres

1. The problem statement, all variables and given/known data
This problem is from Gray and Searle's Electronic Principles:
P1.1 - The MOS transistor characteristics of Fig. 1.8 are a graphical presentation of the functional relationship
$i_{D} = i_{D}(v_{GS},v_{DS} )$
in which $v_{GS}$ is taken as a parameter and $i_{D}$ is plotted against $v_{DS}$. Alternatively, we could display this relationship by taking $v_{DS}$ as a parameter and plotting $i_{D}$ versus $v_{GS}$. The resulting family of curves is called the forward transfer characteristic of the triode.
(a) Use the data of Fig. 1.8 to generate this family of curves. Plot the three curves that correspond to $v_{DS} = 2 volts, 4 volts, and 6 volts. (b) Can a load-line construction analogous to that illustrated in Fig. 1.10 be used with this family of curves? 2. Relevant equations Figure 1.8: Figure 1.9: Figure 1.10: Application of KVL to the output mesh of Figure 1.9 yields:$V_{B} = v_{O} + v_{DS}$or, equivalently,$V_{B}=i_{D}R_{L}+v_{DS}$The intercepts of the load line are: When$v_{DS}=0, i_{D} = \frac{V_{B}}{R_{L}}$and When$i_{D}=0, v_{DS}=V_{B}$3. The attempt at a solution For part (a), I created the LTSpice circuit of an nmos and stepped it by VDS, while sweeping VGS - this gets me the forward transfer characteristic (admittedly there is a difference between the nmos model in LTspice and the output characteristics of the nmos under consideration, but that could be fixed. It's good enough, but more importantly it allows us to get very good values whereas reading values from the graph is not very accurate). I'll affix the LTSpice circuit to this post later. So the question is part (b) - is there a load-line we can construct for the forward transfer characteristic? It doesn't seem like it, because the swept parameter ($v_{GS}$) isn't in the output mesh (whereas$v_{DS}$is). If we set$v_{DS}$to some value, we get a horizontal line for$i_{D}##, because the current through RL is set.

I guess I'm looking for input to see if my thoughts on part (b) are way off?
Thanks all!

2. Jan 7, 2018

PF_Help_Bot

Thanks for the thread! This is an automated courtesy bump. Sorry you aren't generating responses at the moment. Do you have any further information, come to any new conclusions or is it possible to reword the post? The more details the better.