FPGA/CPLD advice appreciated

  • #1
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Dear Sirs,

I'm using Microchip PIC's as programmable laboratory timer among other things, but the 100ns instruction cycles are not adequate anymore. So I thought of beefing it up with a 5M40Z MAX-V CPLD which has 5ns end-to-end delay, bought the programmer and downloaded the Quartus Prime Lite Edition software, and everything came to a grinding halt.

The Quartus toolchain is a piece of eclectic patchwork and it spews out un-googleable error messages with every click of the mouse. I'm not complaining about the Altera Hardware Description Language (AHDL), it's the Integrated Development Environment (IDE) that's the culprit here.

Question: Can anyone suggest some alternatives? It has to be cheap and work out of the box?

Best regards
Abim
 

Answers and Replies

  • #2
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Dear Sirs,

100ns instruction cycles are not adequate anymore.
What timing resolution do you actually require?

P.S. I don't think PF users are required to be male.
 
  • #3
berkeman
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The Quartus toolchain is a piece of eclectic patchwork and it spews out un-googleable error messages with every click of the mouse.
Maybe start a separate thread with some of those errors you are seeing -- we might be able to help you get past them. I have used earlier versions of their toolchains.

BTW, are you using their "lite" version? http://fpgasoftware.intel.com/?edition=lite
 
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  • #4
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What timing resolution do you actually require?
I had chosen 5ns as acceptable, less is even better but then the price unfortunately goes up.

P.S. I don't think PF users are required to be male.
If you are referring to my use of "Dear Sirs" then firstly there is no specific gender requirement in that term, it is a civilized and colloquial greeting when addressing a predominantly male audience, which I believe PF is. As to political correctness I'm siding with Mr. Jordan Peterson.
 
  • #5
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Maybe start a separate thread with some of those errors you are seeing -- we might be able to help you get past them. I have used earlier versions of their toolchains.
If you believe that PF would not suffer from multiple threads about that topic, then I will try and install it again.

BTW, are you using their "lite" version? http://fpgasoftware.intel.com/?edition=lite
Yes, I used the Lite version.
 
  • #6
berkeman
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If you believe that PF would not suffer from multiple threads about that topic, then I will try and install it again.
Oh sorry, did I miss a thread already where you were asking for CPLD/FPGA help? Can you give ma a link?
 
  • #7
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Oh sorry, did I miss a thread already where you were asking for CPLD/FPGA help? Can you give ma a link?
no, I'm asking you if that would be acceptable for PF, I don't want to flood the forum with such commercial product specific questions.
 
  • #8
berkeman
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no, I'm asking you if that would be acceptable for PF, I don't want to flood the forum with such commercial product specific questions.
I think it would be fine. You can post screenshots of what you are trying to do and what errors you are getting. I may download the lite version just to check it out...
 
  • #9
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Dear Sirs,

I'm using Microchip PIC's as programmable laboratory timer among other things, but the 100ns instruction cycles are not adequate anymore. So I thought of beefing it up with a 5M40Z MAX-V CPLD which has 5ns end-to-end delay, bought the programmer and downloaded the Quartus Prime Lite Edition software, and everything came to a grinding halt.
Can you just use faster PICs?

The table at https://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en588853 lists 200 and 252 MHz 32-bit PICs with 4 x 32-bit counter/timers which should meet your 5 ns resolution requirement. Using a fast PIC with a familiar toolchain might offset using a part which is otherwise over-specified for your requirement.


If you are referring to my use of "Dear Sirs" then firstly there is no specific gender requirement in that term, it is a civilized and colloquial greeting when addressing a predominantly male audience, which I believe PF is.
I was. "Sir" is a specifically male greeting (unlike "Guys" - at least in some quarters). Whilst I agree that PF is likely to be predominantly male there's no need to unnecessarily discourage female (or, more generally, non-male) readers. (The make-up of the audience does vary across the various PF fora; there are more female screen names visible in the biology and teaching fora than here in EE.)
 
  • #10
berkeman
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Can you just use faster PICs?
I think the OP is also trying to learn more about electronics in general, so picking up CPLD/FPGA design skills would be a plus. Hopefully the issues he is seeing with the toolchain are just basic user interface and conceptual issues.
 
  • #11
Tom.G
Science Advisor
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I was. "Sir" is a specifically male greeting
Very culture dependent.
 
  • #12
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Can you just use faster PICs?

The table at https://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en588853 lists 200 and 252 MHz 32-bit PICs with 4 x 32-bit counter/timers which should meet your 5 ns resolution requirement. Using a fast PIC with a familiar toolchain might offset using a part which is otherwise over-specified for your requirement.
Yes I could use a faster chip and I did consider that, but then it would be useful only as a timer and not "among other things" e.g. burst read from ADC. With the CPLD I can evaluate a condition and set bit pattern on output all within 5ns, and that would be wonderful if I could do that for just €1 for the chip and €3 for the programmer.

I have also looked at https://tinyfpga.com/ which is sort of the Arduino of FPGA's with a community of users, but the CPLD won me over having more features than a FPGA.

I was. "Sir" is a specifically male greeting
I'm sorry if I didn't make my position clear on the subject of political correctness, please allow me to rephrase: I do not wish to discuss political correctness with anyone on the internet. if I had that desire, there are plenty of other fora where I would have ample opportunity to increase my blood pressure, PF is certainly not the right forum for such desires.
 
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  • #13
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I think the OP is also trying to learn more about electronics in general, so picking up CPLD/FPGA design skills would be a plus. Hopefully the issues he is seeing with the toolchain are just basic user interface and conceptual issues.
One fine day when I was meticulously soldering SMD logic gates to my SMD PIC, I realized that it was a complete waste of time and I had to expand my skill set with CPLD/FPGA design skills.

I will be reverting shortly with a new post as you suggested.
 
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  • #14
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I think the OP is also trying to learn more about electronics in general, so picking up CPLD/FPGA design skills would be a plus. Hopefully the issues he is seeing with the toolchain are just basic user interface and conceptual issues.
OK, so I managed to download and install the Quartus software, make a "Hello World" design and successfully compile it without errors, and that makes me Bob's nephew.

This time the software was available from the intel website, the download was painstakingly slow and cumbersome, but the install went without problems. First it wouldn't launch because of some shared libs missing, fixed that and Quartus popped up on my screen.

Found this hello world guide which I can recommend for first timers.

I noticed that Quartus had evolved to the better since last time I tried it, it's more intuitive and less clutter, so I expect plain sailing from here on. But I reserve my right to post questions when I eventually hit a snag.

Thank you.
 
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  • #15
berkeman
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Great news! :smile:
 
  • #16
eq1
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  • #17
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I've found FTDI modules are great for these types of applications. You can get lots of pins, great data rates, and since the logic runs on the host, complex behaviors, all for little money (~$40). Just a USB port is needed and no IDE. And there is a ton of example code out there in a variety of programming languages.

https://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
Thank you, I had a look at it, unfortunately it's too black-boxy for me, and it is Windows oriented, I'm using Linux.
 
  • #18
rbelli1
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it's too black-boxy for me, and it is Windows oriented, I'm using Linux.
They work on linux too. The biggest problem is that getting sub-ms timing over USB would be wildly optimistic if not downright impossible and that is way slower than you need.

FPGA/CPLD is probably the way to go as you have already found.

BoB
 
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