I've recently purchased an FPGA development board from Digilent, particularly the Spartan 3E-1600 MicroBlaze development board. Back in school, we did some very basic VHDL development with Cypress WARP but ran as simulations. I wanted to expand on that and learn something that the industry uses (on something tangible), so I chose Xilinx FPGA's and Verilog HDL. Their current free development package is the ISE WebPack 13.4 which is what I'm trying to use. I've started with a very basic XOR function with two inputs and one output but it isn't working. For anyone familiar with this development package, my process has been the following: 1.Start a new project and select the 'Spartan-3E 1600E MicroBlaze Dev Board' option (the board I bought) in the Design Properties and hit Ok. 2.Then, add new 'Verilog Module' source. 3. Define the module with In0 and In1 Inputs, and Out0 Output (Direction for these set accordingly). 4. Add 'assign Out0 = In0 ^ In1;' line to the Verilog source (.v file) between module and endmodule. 5. Open PlanAhead and assign my Inputs to 'L13' and 'L14', Output to 'R14'. I also add pullup to the inputs and set output drive to 8. (verified by checking my .ucf file) 6. Run Synthesize - XST, Run Implement Design, then Run Generate Programming File (all check marks). 7. Check .bit file and it is 729KB. I was told by Xilinx customer service that the .bit file shouldn't be this large but I cannot figure out why it is. The board I have has two PROM devices, each 4Mb so the .bit file for this simple XOR will not even fit on one PROM device. I tried programming the FPGA directly with this .bit file and got an unresponsive board and I also tried programming the PROM devices with the .bit file cascaded and programming the FPGA from the PROM, same result (no surprise there). I would greatly appreciate any help that anyone might be able to provide me as I am stumped.