# Help with Op-Amps

#### ENGRstudent

So, here's the deal:

The professor that normally handles Electronics 1 and Electronics 2 went on sabbatical for a year, so the engineering department brought in a guest lecturer to handle it during his absence. The original electronics professor would do op-amps in electronics 1, and BJT's and FETs in electronics 2. The guest lecturer came in and did only BJT's in electronics 1, and now that the resident instructor is back from sabbatical, he's doing BJT's and FETs.

We told him that we hadn't covered a single practical op-amp yet, so he's been trying to use or lab time to condense an entire semester of op-amps into 3 hour periods on wednesday afternoons.

He gave us the attached homework problem on op-amps. What he told us was:

The CMRR of Op-Amps 1 & 2 are equal and are finite.
A) What is the expression for V_out
B) What is the relationship between the various resistors for the output to be proportional to the difference of V1 and V2?

V_out is taken at the node right above R1, as shown by the oscilloscope.

I'm not entirely certain how to approach this problem. In all the examples we've worked in class, I've never seen an op-amp circuit connected this way.

No values were given; he wants the answer in algebraic form.

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#### waht

I suggest you read the "art of electronics" by Horowithz, in just a few pages you can learn everything there is to op-amp.

The golden rule is: The ouput of an op-amp will force the potential difference between 2 inputs to be zero.

If the op-amp can't accomplish that, then the output will swing to either +Vmax or -Vmax.

#### Averagesupernova

Gold Member
Engrstudent: While waht is basically correct, don't take the advice too literally. What he says is absolutely 100% true if the op-amp is running in what is often called 'linear mode'. Sometimes an opamp is run non-linear such as comparators, schmitt triggers, etc. Sometimes even one half of the cycle is one mode and the other half is the other mode. An active clamp would run this way for instance.

#### ENGRstudent

Thank you for the info. We haven't learned anything about nonlinear operation, but I do remember him going over V+ = V- for linear operation.

I'm still unsure as to how I should approach this problem, though.

#### waht

I suppose the nonlinear mode arises when the feeback loop is unable to produce 0 potential difference between the inputs.

So for your circuit you can analyze it like this. If you set v1 to 5 volts, then output pin 3 of U1 will have to force the feedback loop to make the voltage difference between pin 1 and 2 zero, so pin 2 has to be 5 volts also.

If you know R1, or the current, your could calculate the ouput put voltage at 3.

#### berkeman

Mentor
It's a trick question. The outputs of the opamps are shorted together and shorted to ground. Vout = 0V.

With other resistor values and non-zero excitation, then analyze the circuit the way waht is explaining.

#### ENGRstudent

OK, I think I'll be able to figure out an expression showing that Vout = 0. I just ran the simulation in MultiSim, and that is correct. As I understand it, I should use KCL to accomplish this, is that right?

I still need some help with part B of the problem.

#### Paulanddiw

I thought I'd sent this last night, but I don't see it in the thread now. Just as well, what I sent has an error. I hope this doesn't have more than an algebraic error.

BUT, I need a favor. Could you let me know how you got the thumbnail to appear in your first message? Thanks.

Look at it this way. There are two sources of current I1 and I2 from the op-amps. The voltage at the junction between R4 and R3 is V2
$$V2 = R4(I1+I2)$$
The voltage at the junction of R1 and R2 is V1 (because v+=v- of the op-amps).
$$V1 = R2 I1 +R3(I1+I2)+V2$$
The output voltage is:
$$V_ = V1 + R1 I1$$
So, I get:
$$V_ = V1(1+R1/R2)-V2[(1+R3/R4)R1/R2]$$

For the output to be proportional to V1-V2 the coefficients have to be equal:

$$V1(1+R1/R2)= V2[(1+R3/R4)R1/R2]$$

In other words:
$$R1R3 = R2 R4$$

Paul Deichelbohrer

#### ENGRstudent

Thank you for your help, Paul.

You can upload attachments to your post by clicking the "Manage Attachments" button in the "Additional Options" section that appears below your message when you are submitting or editing a new post.

I'm going to sit down this afternoon to work this problem and I will post back if I find any descrepencies between my findings and yours.

#### ENGRstudent

I ran the circuit again in MultiSim, and I've found that Vout is only 0 if all the circuit elements are equal, i.e., V1 = V2, R1 = R2 = R3 = R4. If you change these values, Vout changes accordingly. Berkeman, could you explain to me how this might be correct or incorrect? I am not challenging your statement, I am trying to better understand why it should or shouldn't be 0 at the output.

Paul, I came up with a slightly different answer from what you had. Can you expand your derivation more so that I can see the steps between your answers?

I used superposition to get the following:

Replacing V2 with a short makes U2 an inverting op-amp with respect to V1:

Vout_1 = [(1 + R1/R2)*V1] + [(-R3/R4)*V1]

Vout_1 = V1*[(1 + R1/R2) - (R3/R4)]

Replacing V1 with a short makes U1 an inverting op-amp with respect to V2:

Vout_2 = (1 + R3/R4)*V2 + (-R1/R2)*V2

Vout_2 = V2*[(1 + R3/R4) - (R1/R2)]

Vout = Vout_1 - Vout_2

Vout = V1*[(1 + R1/R2) - (R3/R4)] - V2*[(1 + R3/R4) - (R1/R2)]

I do not understand how you came about your result for part B. Could you please elaborate?

I very well may be way off the mark, and if so, please tell me!

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#### Paulanddiw

Great problem!

You know, I see how setting v2 =0 (shorting to ground) makes U2 an inverting op-amp, but I don't see what you mean "with respect to v1". To me, setting v2=0 makes the voltage on both sides of R4=0, and, therefore, I don't see how the value of R4 can appear in your expression for vout_1.

With v2=0, there will be no current in R4. Since the input impedance of op-amps is very high, there will be no current in R3 either. In this case, I1=-I2. Since the voltage at the junction between R1 and R2 is V1, the current in R2 will be I1=V1/R2. Since the output voltage is I1R1+V2, using this value for I1, I get that Vout_1 = v1(1+R1/R2).

Maybe you could give me some more details on how you got your value.

As for part B, if the output voltage is going to be proportionat to V1-V2, look at it this way:

V_ = k(V1-V2) = kV1- kV2
where k is some coefficient of proportionality.

In your (or mine, for that matter) expressions for the output in terms of V1 and V2 we get some expression in R1, R2, etc. for the coefficients of V1 and v2. Like it show above, both expressions have to be equal for the result to be proportional to v1-v2.

Thanks for helping me with the thumbnail.

Let me know if there's more to do on this problem.

#### ENGRstudent

Replace "with respect to" with "due to the signal from" in my last post. It's just a different way of saying it.

I don't see how setting V2 = 0 would make the current through R4 and R3 = 0 also. There is still a voltage in the circuit from V1 and a current that must still travel to ground, and because the input impedance of the op-amp is so high, I don't think it would be able to go through the shorted V2 line; it would have to travel through R4, wouldn't it? There is still a voltage from V1 that is applied to all of the resistors when V2 is replaced with a short.

The voltage at the node right above R4 is what I was referring to when I said that U2 would be an inverting op-amp due to the signal from V1. The signal from V1 goes into the V- terminal of U2, which is where I got the (-R3/R4) term.

I very well may just have a fundamental misunderstanding of op-amp operation, too. That's why I'm here trying to figure things out.

Thank you for taking some time to help me. I hope we can reach a conclusion that makes sense to both of us!

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#### Paulanddiw

The current from the v1 circuit (coming from R2) goes into U2, i.e., the output current of U2 is -v1/R2. If any current went through R3, the negative input of U2 would be non-zero and then the high gain of the Op-amp would try to be very negative and suck in lots of current. It sucks in only -v1/R2, this is just enough to keep it's negative input =0.

Attached are a couple sketches of op-amp circuits. (I hope a thumbnail appears.) In sketch 1 the output of the op-amp is obviously zero. In sketch 2 it is still zero. The current supplied by the 4.9v through R2 is absorbed by the op-amp to prevent any voltage from appearing on its negative input.

If is not clear, let me know and I'll show you another way to look at it.

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#### ENGRstudent

OK, I think I need to take a step back and look at this from a broader viewpoint.

Could you please explain how you derived your expression for Vout in your first post? I'm having trouble seeing how you came up with your equations, and I'm not sure which currents from which branches you've labeled I1 and I2, and I just don't see how you went from step 3 to step 4 in your derivation.

Thank you again for your patience.

#### Paulanddiw

In my post, there is no thumbnail. (I wanted a thumbnail to appear in my post). I drew the sketches in my drafting program, and cut/pasted the drawing into MS Word. Then I saved MS Word file so I could call it up to be attached to my post.

Should I have used something other than MS Word?

There are only two sources of current, the op-amps. I called the current from U1, I1, and the current from U2, I2. I assume there is no current in the lead to the oscilloscope nor in the leads to the negative inputs to the op-amps.

You HAVE to believe that v+=v- for the op-amps. Therefore, the junction between R1 and R2 is at voltage v2. Op-amp U1 produces current I1 which produces a drop across R1, so the voltage at the oscilloscope (output voltage) has to be v1+R1 I1. (~~~)

I1 goes through R2, so the output terminal of U2 has to be at voltage v1-I1 R2.

Through R3 we have both I1 and I2 flowing so the voltage at the junction between R4 and R3 has to be below that of U2's output terminal by an amount R3(I1+I2). However, this point (junction between R4 and R3) is at voltage v2 because v+=v- for U2 (just as it was for U1). So I sum the voltage drops to get:

v1=R2 I1 + R3(I1+I2) + v2. (****)

Both I1 and I2 flow through R4, so v2 = R4(I1+I2).

To solve these, first, I solve for:
I1+I2 = v2/R4

I substitute this expression into Eq. (*****):

v1=R2 I1 + R3(v2/R4) + v2

From this I get I1:

I1 = (v1-v2 - v2 R3/R4)/R2 = v1/R2 - v2(1+R3/R4)/R2

Like I said back at (~~~~), the output (v_) is v1+I1 R1, so,

v_ = v1+v1R1/R2-v2 R1(1+R3/R4)/R2
= v1(1+R1/R2) - v2(1+R3/R4)(R1/R2) (&&&&&&&&&)

I believe this is the expression I had for output voltage in my post of 4/19.

For the output voltage to be proportional to v1-v2, the relationship has to have the form:

v_ = k(v1-v2) where k is some constant of proportionality.

Multiplying this out:
v_ = kv1 - kv2

Comparing this expression with &&&&&&&&:

k has to be equal to (1+R1/R2) and also (1+R3/R4) (R1/R2). In otherwords, both expressions have to be equal to each other:

1+R1/R2 = (1+R3/R4)(R1/R2)

Multiplying this out:

1+R1/R2 = R1/R2 + (R1R3)/(R2R4)

canceling R1/R2 from both sides:

1 = (R1R3)/(R2R4)

Multplying by R2R4, I get:

R2 R4 = R1 R3

I hope this helps. Let me know if it does or doesn't. Also, let me know what I'm doing wrong to get a thumbnail on my post.

Thanks.

Paul

#### ENGRstudent

I think I'm starting to see. Thank you, Paul. I understand how you came about your derivations; I still think I have more to learn about how to evaluate op-amp circuits.

This assignment isn't for a grade, it's just to give us some practice work. I will speak with my instructor tomorrow to see if he can help me some more.

As for the thumbnail, I misunderstood what you were asking - I thought you just wanted to know how to upload an attachment. For a thumbnail, you need to save your file as either a JPEG or a bitmap file before you upload it to the website.

Thank you again for your patience and persistence.

If anyone else has anything to contribute that might aid my understanding, please don't hesitate!

#### Paulanddiw

Thanks for the fun. And thanks for the information about thumbnail.

#### ENGRstudent

Well Paul, it looks like I still need some help :).

I tried analyzing the circuit writing 3 KCL equations (1 for the node between R1 & R2, 1 for the node between R2 & R3, and 1 at the node between R3 & R4), and I was able to get the same answer as you. I was happy with that.

Then I went and spoke to my prof., and he pointed out that an important consideration was neglected: these are not ideal op-amps

He said that the CMRR must be taken into account for these calculations, and sort of told me how to look at it, but I think I'll still need some help.

Any ideas as to how approach this?

#### Paulanddiw

OK, CMRR stands for what? Common Mode Rejection Ratio? How does the output change as the common-mode voltage goes up/down? I may have known this years ago, but, fill me in.

Thanks.

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