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Help with state machine

  1. Jun 22, 2010 #1
    This is my first state machine that has an input large than one bit. The simulation tool says that I synthesize my output away. I think I understand why, but dont really know how to fix it.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    --
    entity trimoore is
    port
    (
    clk : in std_logic;
    x : in std_logic_vector (1 downto 0);
    ------ mode : in std_logic_vector (2 downto 0);
    q : out std_logic_vector(2 downto 0)
    );
    end trimoore;
    --
    architecture behave of trimoore is

    type state_type is (A, B, C);
    signal state: state_type;
    begin
    process (clk)
    begin

    if (clk'event and clk ='1') then
    case state is
    when A =>
    if x<="11" then state <= A;
    else state <= B;
    end if;
    when B =>
    if x <= "11" then state <= A;
    elsif x <= "00" then state <= B;
    else state <= C;
    end if;
    when C =>
    if x <= "00" then state <= B;
    elsif x <= "01" then state <= C;
    else state <= A;
    end if;
    end case;
    end if;
    end process;

    with state select
    q <= "000" when A,
    "001" when B,
    "110" when C;
     
  2. jcsd
  3. Jun 22, 2010 #2

    berkeman

    User Avatar

    Staff: Mentor


    Can you post a state diagram that goes with the code? That would make it easier to try to see what is getting optimized out.
     
  4. Jun 22, 2010 #3
    10 is a dont care input. I have attached a pdf of the state diagram. Also, I want three seperate iterations of this to be selected from a three bit input. Could I do case statements for entire state machines? thanks ahead of time. actual output is wrong...sorry. the real problem is that the states dont change in simulation.
     

    Attached Files:

  5. Jun 22, 2010 #4
    I also get a warning stating that input x does not drive logic. the code is correct to my understanding. Could this maybe be the compiler?
     
  6. Jun 23, 2010 #5
    OK, I'm more of Verilog person and might be wrong, but let me tell you what I observe.

    1. you use "if x<=00 then ...". Isn't <= for assignment ?(Again I'm not VHDL person, so forgive me).
    2. What does the following mean ?

    when A =>
    if x<="11" then state <= A;
    else state <= B;

    Does it mean when you are in state A and X=11, it stays in A, otherwise goes to B ? if so, it doesn't match the state diagram you posted. The same for B and C too.

    3. Regarding stating all the possible states, it probably depends on the compiler. In Verilog, it is always recommended to put all the possible states(even with default statement) to avoid the latch inference.

    4. Your output is q. You didn't assign anything to q in the code so the tool thinks it can optimize it away. Assuming from the name, you're trying to make a Moore machine. You need to assign the value to q based on the current state.
     
    Last edited: Jun 23, 2010
  7. Jun 24, 2010 #6
    About the only advice I could give (I'm a verilog person as well) is that I normally will separate the actual register assignments , (the clocked state memory) from the continuous assignments or the next state logic. This will also help or force the compiler to choose a one hot state machine or not. L
     
  8. Jul 12, 2010 #7
    sorry for the delayed replies.

    I used a different compiler, and everything came out fine. I would like to addres the questions that were asked though.

    I made a horrible mistake of posting the wrong version of the code, and that is why is does not match the state diagram.

    To lostinxlation: you are correct in your interpretation of the VHDL for the states, but the q is assigned values through the select statements at the end of the code.

    To lifeattthesha: i had tried to seperate them before, but I was getting errors. Turns out that the Quartus free edition that I had been using from school, needed a vouple of updates. I used the trial of Xilinx ISE and everyhting worked fine.

    Thanks for the input from both!
     
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