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Hexadecimal number on seven-segment

  1. Oct 6, 2011 #1
    I need to design a bank of four 4-bit registers whose contents are displayed on the seven-segment displays. So, basically just display 4 hexadecimal numbers on the 7-segment. The output switches on its own with every clock cycle. I'm using a Basys2 board for this. This is what I have so far...

    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity Register_Bank is
    port( x: in std_logic_vector(3 downto 0);
            disp_en: out std_logic_vector(3 downto 0);
            z:  out std_logic_vector(7 downto 0);
            ck,reset: in std_logic);
    end Register_Bank;

    architecture Behavioral of Register_Bank is

    Type my_state is(s0,s1,s2,s3);
    Signal n_s: my_state;
    Signal ck_div: std_logic;
    Signal temp,temp1,temp2,temp3,temp0,temp_main: std_logic_vector(0 to 3);
    Signal R0,R1,R2,R3 : std_logic_vector(3 downto 0);

    begin

    --
    process(temp_main)
    begin
    case temp_main is
        when "0000" => z <= "00000011";
        when "0001" => z <= "10011111";
        when "0010" => z <= "00100101";
        when "0011" => z <= "00001101";
        when "0100" => z <= "10011001";
        when "0101" => z <= "01001001";
        when "0110" => z <= "01000001";
        when "0111" => z <= "00011111";
        when "1000" => z <= "00000001";
        when "1001" => z <= "00001001";
        when "1010" => z <= "00010001";
        when "1011" => z <= "11000001";
        when "1100" => z <= "01100011";
        when "1101" => z <= "10000101";
        when "1110" => z <= "01100001";
        when "1111" => z <= "01110001";
        when others => null;

    --temp3 <= x<3>;
    --temp2 <= x<2>;
    --temp1 <= x<1>;
    --temp0 <= x<0>;

    --wiring the register contents to outputs
    temp3 <= R3;
    temp2 <= R2;
    temp1 <= R1;
    temp0 <= R0;

    --state machine for TMD
    Process(x,ck_div)
    begin
    if ck_div ='1' and ck_div'event then
    case n_s is
        when s0 =>
            temp <= x<0>;
            disp_en <= "0111";
            n_s <= s1;
        when s1 =>
            temp <= x<1>;
            disp_en <= "1011";
            n_s <= s2;
        when s2 =>
            temp <= x<2>;
            disp_en <= "1101";
            n_s <= s3;
        when s3 =>
            temp <= x<3>;
            disp_en <= "1110";
            n_s <= s0;  
    end case;
    end if;
    end process;

    -- clock division
    process(ck)
    variable count: integer;
    begin
    if ck ='1' and ck'event then
        if reset ='1' then
            count := 0;
            ck_div <= '0';
        elsif reset ='0' then
            if count = 999999 then
                ck_div <= not ck_div;
                count := 0;
            else
                count := count + 1;
            end if;
        end if;
    end if;
    end process;    

    end Behavioral;

    I know the logic is off and there are syntactical errors as well. I need help trying to debug this. I'd greatly appreciate help!
    1. The problem statement, all variables and given/known data



    2. Relevant equations



    3. The attempt at a solution
     
  2. jcsd
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