How to improve synchronous counter

  • Thread starter KillaKem
  • Start date
  • #1
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Assume a synchronous counter with the following counting
sequence:
0 -> 1 -> 3 -> 2 -> 4 -> 6 -> 5 -> 7 -> 0

1.Produce the above counter next state equations.

2.Using positive-edge D-type flip-flops, 2-input OR and 2-input AND gates, sketch the circuit diagram of the above counter.

3.Given that, a D-type flip-flop has TPHL= 10 ns, TPLH= 8 ns, Tsu=2 ns, a 2-input AND gate has propagation delay of 3 ns, and a 2-input OR gate has propagation delay of 5 ns, estimate the maximum clock frequency at which the above counter could operate.

4.Describe how the complexity of the given counter could be reduced by using a different count sequence.

****I have done the first three questions, the only problem I have is in answering the last question.I really don't understand what the question is looking for.
 

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