Solving SR Latch: Get 2nd Input from NOR Gates

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In summary, the conversation is about using an image to understand how to get the second input in an S-R latch when it has to come from the output of NOR gates. The image shows a basic memory cell with two inputs, S and R, that cannot be both TRUE at the same time. The input that is not connected to the NOR gate does not affect the output. The conversation also includes a discussion about the S-R latch's stable states and how it remembers the last state. The conversation then moves on to a practice problem involving solving for Qt+1, with various combinations of inputs and the enable bit. The final question involves clarifying the state of the S-R latch when both S and R are equal to 1, which
  • #1
whitehorsey
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1. http://forum.allaboutcircuits.com/image_cache/httpwww.cs.nyu.educoursesfall00V22.0436001lecturesfigssrlatch.png

Using this image, how would you get the second input if the second input has to come from the output of the nor gates?
 
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  • #2
whitehorsey said:
Using this image, how would you get the second input if the second input has to come from the output of the nor gates?
I don't understand what you are asking? Do you even understand what you are asking? :confused:

The S-R latch is a basic memory cell. S and R cannot* both simultaneously be TRUE. Provided only one of R and S is TRUE, this forces the cell to take up one of two stable memory states. When that input returns to FALSE, meaning both inputs are now FALSE, the cell remembers that last state.

Now, what was your question? http://imageshack.us/a/img402/3247/undecidedg.gif
 
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  • #3
NascentOxygen said:
I don't understand what you are asking? Do you even understand what you are asking? :confused:

The S-R latch is a basic memory cell. S and R cannot* both simultaneously be TRUE. Provided only one of R and S is TRUE, this forces the cell to take up one of two stable memory states. When that input returns to FALSE, meaning both inputs are now FALSE, the cell remembers that last state.

Now, what was your question? http://imageshack.us/a/img402/3247/undecidedg.gif

Ah my question is because the nor gate needs two inputs what is the other input the one that belongs to the criss crossed line. So if S = 1 what is the other input that is going into the nor gate with it?
 
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  • #4
whitehorsey said:
So if S = 1 what is the other input that is going into the nor gate with it?

It doesn't matter. The result out of the NOR gate will be zero.

When S and R are both zero, the output is in a stable state with Q and /Q being complements of each other. If for some reason Q and /Q are the same (both 1 or both 0), the state immediately changes to 1/0 with the fastest NOR gate deciding which will be 1 and which will be 0.
 
  • #5
whitehorsey said:
Ah my question is because the nor gate needs two inputs what is the other input the one that belongs to the criss crossed line. So if S = 1 what is the other input that is going into the nor gate with it?

The second input is ¬Q. Maybe it's 1, maybe it's 0. Try both, one at a time.
 
  • #6
Ah my question is because the nor gate needs two inputs what is the other input the one that belongs to the criss crossed line. So if S = 1 what is the other input that is going into the nor gate with it?

The short answer is that the other input is Q but its state doesn't matter.

Longer answer...

So you asked what happens with S=1... Follow it around the circuit step by step...

If S=1 then Qbar = 0 whatever the other input is. Draw the truth table for a NOR gate.

Then if R=0 the inputs to the top gate are R=0 and Qbar=0 so the output Q=1.

If Q=1 then the two inputs at the lower gate are S=1 and Q=1 so the output Qbar = 0

If you then set S back to 0 the circuit will stay ("remember") Q=1 and Qbar=0. That's why S stands for "Set". It sets Q=1.

By symetry if you pulse R from 0 to 1 and back you get Q=0, and Qbar = 1 which is why R stands for "Reset".

So the truth table is...

RS Q Qbar
------------
00 Q and Qbar remember their state
01 Q=1, Qbar=0
10 Q=0, Qbar=1

It is possible to have RS=11 in which case Q=0 and Qbar=0 but if RS change back from 11 to 00 at exactly the same time you can't predict how Q and Qbar will end up. If they change at different times the last one remaining at logic 1 "wins".
 
  • #7
CWatters said:
The short answer is that the other input is Q but its state doesn't matter.

NascentOxygen said:
The second input is ¬Q. Maybe it's 1, maybe it's 0. Try both, one at a time.

aralbrec said:
It doesn't matter. The result out of the NOR gate will be zero.

When S and R are both zero, the output is in a stable state with Q and /Q being complements of each other. If for some reason Q and /Q are the same (both 1 or both 0), the state immediately changes to 1/0 with the fastest NOR gate deciding which will be 1 and which will be 0.

Thank You for your responses! So then I tried working on some practice problems I found on the internet but there's one that I'm stuck on.

219ubzb.jpg


E Qt St Rt Qt+1
0 0 0 0 Qt
...
1 0 0 0 0
1 0 1 1 undefined
1 0 1 0 1
1 1 0 0 Qt In this problem, you have to solve for Qt+1.
The answers I got was Qt whenever the Enable was equal to 0. I also got Qt with the second one and fourth and fifth one. Yet, the second one is equal to 0, the fourth one is equal 1 and the fifth one is equal to Qt. (Answers that came with this problem) Why is that?Also, just to make sure if I understand a part about SR Latch is that whenever S and R = 1 the state would always be undefined?
 
  • #8
whitehorsey said:
Also, just to make sure if I understand a part about SR Latch is that whenever S and R = 1 the state would always be undefined?
Precisely what state are we talking about?

If your question involves what are the gates' outputs when S=R=1, then you should be able to work that out. What is the output of any NOR gate when an input equals 1?

Maybe your question is about something else?
 

1. What is a SR latch?

A SR latch, also known as a Set-Reset latch, is a type of electronic circuit that can store one bit of information. It has two inputs, S (set) and R (reset), and two outputs, Q and Q̅ (the inverse of Q). It is commonly used in digital systems for storing memory or controlling logic circuits.

2. How does a SR latch work?

A SR latch is made up of two cross-coupled NOR gates. When the S input is set to 1 and the R input is set to 0, the Q output will be set to 1 and the Q̅ output will be set to 0. Conversely, when the S input is set to 0 and the R input is set to 1, the Q output will be set to 0 and the Q̅ output will be set to 1. This allows the latch to store one bit of information, with the state being determined by the inputs.

3. How can I get the second input for a SR latch from NOR gates?

To get the second input for a SR latch from NOR gates, you can use the following circuit: connect the output of one NOR gate to the S input of the latch, and the output of the other NOR gate to the R input of the latch. This will allow the NOR gates to control the state of the latch, with one gate acting as the set input and the other as the reset input.

4. What are the advantages of using NOR gates for a SR latch?

Using NOR gates for a SR latch has several advantages. Firstly, NOR gates are readily available and commonly used in digital systems. They also have the property of being able to act as both AND and OR gates, which allows for flexibility in circuit design. Additionally, using NOR gates can result in a simpler and more compact circuit compared to using other logic gates.

5. Are there any limitations to using NOR gates for a SR latch?

While NOR gates have several advantages for use in a SR latch, there are also some limitations. One limitation is that NOR gates can only handle two inputs, so more gates may be needed for latches with multiple inputs. Additionally, NOR gates can introduce a small delay in the circuit, which may need to be taken into account in certain applications.

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