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I need help in VHDL synthesis

  1. Nov 24, 2007 #1
    Hello, everyone!Now I'm studying VHDL, and our teacher gave us some questions as follows:
    1. Complete the following code fragment and try to synthesize the VHDL:
    process begin
    wait until Clk = '1';
    Phase <= "0" after 0 ns; Phase <= "1" after 10 ns;
    end process;
    What is the error message? Synthesize this code, and explain the results:
    process begin
    wait until Clk_x_2 = '1';
    case (Phase) is
    when '0' => Phase <= '1'; when others => Phase <= '0';
    end case;
    end process;

    2.Consider the following processes:
    S1: process (clk) begin
    if clk'EVENT and clk = '1' then count <= count + inc; end if;
    end process;
    S2: process (clk) begin
    if rst = '1' then count <= 0;
    elsif clk'EVENT and clk = '1' then count <= count + inc;
    end if;
    end process;
    S3: process (clk, rst) begin
    if rst = '1' then count <= 0; elsif clk'EVENT and clk = '1' then
    count <= count + inc; sum <= count + sum;
    end if;
    end process;
    S4: process (clk) begin
    if clk'EVENT and clk = '1' then if rst = '1' then count <= 0;
    else count <= count + inc; end if;
    end if;
    end process;
    S5: process (clk, rst) begin
    if rst = '1' then count <= 0;
    elsif clk'EVENT and clk = '1' then count <= count + inc;
    else count <= count + 1;
    end if;
    end process;
    S6: process (clk, rst) begin
    if rst = '1' then count <= 0;
    elsif clk'EVENT and clk = '1' then count <= count + inc;
    end if; inc <= not dec;
    end process;
    Write code to drive each of these processes and simulate them. Explain any errors or problems you encounter. Try to synthesize your code and check that the results behave correctly and match the simulation results. Explain any differences in behavior or any problems you encounter.

    For these two questions, I have n o idea about them, is there anyone could help me?
     
  2. jcsd
  3. Nov 25, 2007 #2
    1) A process without a sensitivity list is useless. If you don't know what the sensitivity list does...well...the way I think of it is: if there is a change on the variables in the sensitivity list, the process will execute. example:

    Process(A)
    begin
    X <= B and A;
    end process;

    that means that if B changes at any time...nothing will happen..if X changes at any time nothing will happen...but if A changes...X gets updated (the process executes)
     
  4. Nov 26, 2007 #3
    Thanks for your help
    I have finished part of them,but I met one problem when I write VHDL to test code s5
    Here is my code and the error message( I used Quartus II version 7.0 to synthesis):
     for s5
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity cnt4 is
    Port (clk : in std_logic;
    rst: in std_logic;
    inc: in std_logic_vector(3 downto 0);
    count: buffer std_logic_vector(3 downto 0));
    end entity cnt4;

    architecture Behavioral of cnt4 is
    begin process (clk, rst)
    begin
    if rst = '1' then
    count <= "0000";
    elsif clk'EVENT and clk = '1' then
    count <= count + inc;
    else
    count <= count + "0001";
    end if;
    end process;
    end Behavioral;

    The error message is
    Error (10818): Netlist error at cnt4.vhd(15): can't infer register for count[0] because it does not hold its value outside the clock edge
    Error (10818): Netlist error at cnt4.vhd(15): can't infer register for count[1] because it does not hold its value outside the clock edge
    Error (10818): Netlist error at cnt4.vhd(15): can't infer register for count[2] because it does not hold its value outside the clock edge
    Error (10818): Netlist error at cnt4.vhd(15): can't infer register for count[3] because it does not hold its value outside the clock edge
    Error (10822): HDL error at cnt4.vhd(17): couldn't implement registers for assignments on this clock edge

    I want to know what's the problem?It seems to me everything is all right :(
     
  5. Nov 26, 2007 #4
    I'm no expert here, that's for sure. but from my experience, many devices can't support dual clocking styles. But in theory VHDL can do a lot of things that a particular device can't do. I think the problem with this code is that you're trying to update a register (buffer in this case) on both a rising clock edge AND else (basically a falling clock edge). With most devices it's either one or the other, but not both in a single process.
     
  6. Nov 27, 2007 #5
    A register can be sensitive for only 1 edge of the clock signal.But in that code we deal with both rising edge and declining edge(or others),i think that is the problem.^_^
     
  7. Nov 28, 2007 #6
    Thanks for all of your help and your patient and kindness! I don't know how to express that,Thank you!
     
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