I need help with verilog asap.

  • Thread starter david90
  • Start date
  • #1
305
1
I'm getting this error a lot now and i'm not sure why

WARNING:Xst:524 - All outputs of the instance <N1> of the block <clkdiv> are unconnected in block <pwm>

here's my code

module pwm(clk,in,pwm_out);
input clk;
input [7:0] in;
output pwm_out;

clkdiv N1(clk,gclk);

reg i,pwm_out;

always @(posedge gclk)
begin
for(i=0; i <=255; i=i+1)
begin
pwm_out<=1;
end

end
endmodule
====================

As far as I can tell, gclk is used in the always statement so why xilinix say "unconnected in block <pwm>"?
 

Answers and Replies

  • #3
305
1
thanks for responding. I've been getting a lot of those unconnected warnings so it must be a bad habit that I don't know about. I just wnana figure out what i've been doing wrong. Can u edit the code so that it can syn without the warnings? the code doesn't do anything in particular.
here is the clkdiv module.
---------------------
module clkdiv(clk,gclk);
input clk;
output gclk;
reg gclk;
reg [26:0] counter;
initial counter=0;
initial gclk=0;
always @(posedge clk)
begin
counter = counter +1;
if(counter == 5) //50000000
begin
gclk= ~gclk;
counter =0;
end
end
endmodule
 
Last edited:
  • #4
53
0
I did a visual inspection of both files and I don't see any syntax errors
but I do see one logical error (pwm_out is never set low). To be sure
I compiled both and no errors or warnings were produced.

I am not familiar with the Xilinx verilog compiler (I only use ISE to place
and route edifs) but I would guess the problem is due to the fact that
the compiler cannot find the definition of the clkdiv module when it is
compiling the pwm module. So it doesn't figure out that clkdiv::gclk is
an output.

Are you using the gui to manage the xilinx project? If so make sure you
followed thier produce to add files to the project exactly.
If you are using the command line tool then you probably have to add
each module to the command line and clkdiv has to come first (I would
do this once in a script.)
 

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