Impedance matching!

  • Thread starter bigzuo
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  • #1
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if i want to connect a comparator chip's output (TTL) to Spartan2 FPGA board, can i directly do it, do i need to consider the impedance match? when i directly connect them, I will see the transition on the edge of the waveform stored (after FPGA processing, i save the output of FPGA and plot on matlab) but when i terminate some resistors between them, these transition will become less( up to resistor's value), then let's say i found 1 kohm will sort out this problem, but only sometimes, not always, the other time the transition will appear again! i have no idea about this problem, could someone give me a clue. Thanks a lot!
 

Answers and Replies

  • #2
chroot
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I don't know what you mean by "transition," but I gather it's some kind of effect you're looking to avoid.

The Spartan II FPGA inputs can be configured for a wide variety of signalling standards, TTL included. Make sure the inputs are configured properly, and you should have no problem directly connecting a TTL device to it. The impedance of any reasonably good output driver is very low, and the impedance of any reasonably good input is very high. Obviously, you don't want to match them!

- Warren
 
  • #3
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Firstly I recommend following chroot's advice and insure your IOB is really TTL by checking the ISE par pad report.

Next I recommend measuring the voltage difference between the chip grounds. Especially if they are on different evaluation boards or bread boards. They could easily be off by 100s of mV causing the output of the part to near the thresholds VOLmax or VOHmin of the FPGA. While you are there, run your system and measure the power voltages. While the system is running insure you have stable (measure the AC voltage) valid (measure the DC voltage) levels.

If you have clean power and are using a TTL IOB then you may have transmission line problems. The severity of impedances mismatches and the slew of other problem which arise at higher frequencies are all related to the rise time of the signal. Therefore the best and easiest way to make them go away is to add a low pass filter (using resistors and capacitors in the standard way) to the output of the driver and slow the rise time down (i.e. remove the high frequencies of the signal).

Choosing the time constant is the hard part. Basically the bigger you can make the time constant the less noise you will see on the signal. I'd go with 25% of the sample time and look at the signal. If it is still experiencing enough noise to cause a false sampling I would increase rise time by increasing the sample time (aka lower the sample rate).

Of course there are other options, terminations, etc, but they are much more difficult to get right. So it will boil down to how important is the high sample rate really...
 
  • #4
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Oh ya. Is the output of this comparator synchronous? If it is asynchronous, which I bet it is, and you are not synchronizing the output after taking a large number of samples, the probability of synchronization failures occuring is very high.
This article covers the subject in enough detail to get something working...
http://www.edn.com/article/CA310388.html
 

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