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Inner workings of a semiconductor transistor

  1. May 4, 2005 #1

    I'm doing research to chipproduction, and I can't seem to figure out how transistors really work (in detail). I'm looking at this CMOS inverter gate for example: http://people.deas.harvard.edu/~jones/es154/assigns/prob_assign_01/prob_assign_5_01/cmos_1.gif [Broken]
    More detailed: http://www.scudc.scu.edu/mentortu/pic/spice1.gif

    Chips provide a high- and low-voltage rail (low being ground, high often being refered to as V-DD). What I know about voltage is that it can be regarded as the pressure behind electron flow. So to me, it seems that 0 Volt would mean a complete lack of flow. In this CMOS inverter gate image, the input is either a high or low voltage which controls 2 transistors (NMOS and PMOS), which act opposite from eachother. If one is open, the other one is closed. If a low voltage signal is provided, the top transistor will close, and electrons will flow from the high-voltage rail (V-DD) to the gate output (V-Out).

    What I don't understand is, if low voltage is a total lack of electron flow, why is there any need for a ground-rail? If the top transistor in this image is open (no conduction), wouldn't it automatically be a 0-volt situation because electrons won't flow?

    The way I see it, in the binary system, a 1 (high-voltage) means flowing electrons and 0 (0 Volts) means no flowing electrons. But maybe I've got this all wrong. I'm no physics major and I don't know too much about electric circuits, so there's probably some fundamental information missing, that I have no idea about.

    Is there anyone who could shed some light on this? Thanks very much in advance.

    Somebody seemed to have moved this thread to the Quantum Physics topic (I don't see what Q.P. would have to do with this though).
    Last edited by a moderator: May 2, 2017
  2. jcsd
  3. May 4, 2005 #2
    This may be explained through QM, however your problem is very simple. When we say "voltage", we implicitly mean difference of voltage. For example, the voltage VDD is the difference of voltage between the point called VDD in your schematic and the point ground (GND or VSS). Therefore, when the upper transistor is in the opened state, if the lower transistor is opened or not present, we have not a defined voltage (respectively to GND or VSS) at the output stage of the inverter.
    Therefore if you connect another circuit to this opened output, the new circuit does not know the voltage this inverter delivers (we have a floating input). In other words, this new circuit may see any voltage (it depends mainly on the input stage characteristics of this new circuit and not the opened state of the CMOS inverter, if the lower transistor is also opened).

    Last edited: May 4, 2005
  4. May 4, 2005 #3
    Thanks for your reply. I'm still having trouble understanding it. I don't understand that you say it's an undefined voltage if there's no connection to GND. If there is no voltage source, isn't the voltage 0 (i.e.: no flow of electrons) ? Doesn't the inverter deliver "zero flow" of electrons when the upper transistor is open and the lower transistor non-existant? Does GND not equal 0 Volts? I'm trying to understand everything in terms of "electron flow", and right now, it still doesn't make too much sense :/
  5. May 4, 2005 #4
    In fact, you are trying to use the ohm law: U=RI (where I is your current flow, U the voltage). Not having a current flow does not mean that you have a 0 voltage. Take for example the voltage difference at the pins of an unconnected battery.
    Let's return to your modified inverter driving another hypothetic inverter. Suppose that the opened upper transistor has a very very small leakage current (like in our real life) and that we have not the transistor connected to the ground.
    Now, I suppose you know that the input of a CMOS inverter has a very very huge resistance connected to the ground (or if you prefer, It allows the entry of a very very small leakage current). If you connect the output of your modified CMOS inverter to this CMOS, the leakage current goes through the very very huge resistance and results in a voltage (with reference to the ground of the new inverter): U=RI= (very very huge) times (very very small) => you may have any voltage at the input of this new inverter. In other words, this new inverter may see any voltage depending only on its own characteristics (the huge resistance) and not on the “supposed 0 voltage state”
    Now, if the lower transistor is connected to the ground (very small resistance), this transistor creates a short circuit (all the very very small leakage current of the upper goes trough this transistor) => U=0.

  6. May 4, 2005 #5
    Thanks, it makes a lot more sense already. Although a new weird thing (but not trivial for my problem) arrises:

    U = R * I
    And you say "not having a current flow does not mean that you have a 0 voltage". But if I is 0, U will be 0 as well in this equation. But nevermind that, because I do understand your battery example. In an unconnected battery there is a voltage difference (the pushing and pulling forces), but there's nowhere for the electrons to flow (because there is no circuit). Voltage, but no current, right?

    I did not know anything about high resistance placed around transistors by the way. Is that what the 10P thing is in the image? (I thought a resistor was a zigzag-symbol, not 2 parallel lines). If this is a resistor then let me rephrase what happens according to how I understand it now:

    the high voltage line will leak a tiny bit of current when opened. When this happens without a connection to the ground, the only direction it could go is through the high resistor at the output, which will create a "1" (high voltage, despite the low amount of electrons and high resistance) on the line. If there is a ground connection as well, the electrons will flow in the direction of the least resistance and will leak into the ground, thereby not disturbing the output signal of the inverter gate.

    Is that how it works?

    By the way, does this mean that if leaking current can be stopped (say, with nanotubes or something), the ground rail could some day disappear from chips?
  7. May 4, 2005 #6

    If fact, what you have selected in your schematic is a capacitor (a good model for an input CMOS circuitry equivalent standard charge). Therefore, it is somewhat more complicated.
    However, what you say is true in the DC level approximation (sufficient for this stuff): at the DC level, a capacitor is a very very huge resistor (like a cmos input circuit).

    Yes. Bravo!

    Yes and this has been done a very very long time ago (at the very beginning of the IC industry ; ) , with the TTL technology and some CMOS circuits: the open collector output. Instead of the lower transistor, we remove the upper transistor.
    When we connect directly this type of circuit to a TTL technology based circuit, an open transistor is viewed by the TTL input gate as a one and a closed transistor as a 0. This works because TTL inputs measure current rather than voltage (i.e. they have a very lower input resistance compared with CMOS).
    Therefore, instead of having an output resistor with a very very large resistance, it is easier to choose an input circuitry with a very lower resistance input.

    Last edited: May 4, 2005
  8. May 4, 2005 #7
    Thanks so much :) You've been a great help! :)
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