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Input & Output Impedance

  1. Dec 4, 2007 #1
    hi
    i have one quiry related to input & output impedance of any circuit?
    generally for cascading we expect High Input impedance & Low output impedance to avod loading effect?
    But what is loading effect ? exactly what happen to current & voltage when loading ouucures ?

    how this theory support Maximum Power Transfer theorem ??

    Plz. Help Me
     
  2. jcsd
  3. Dec 5, 2007 #2

    berkeman

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    Staff: Mentor

    All you have to do is write the equations for the voltage transfer through the finite output impedance and into the finite input impedance. Can you show us what those equations look like, and how the resulting voltage transfer ratio is altered from the ideal case?

    Tell us what you know about the maximum transfer of power. How would you go about writing some equations and solving them to figure out what relationship between Zo and Zi gives the maximum transfer of power?
     
  4. Dec 6, 2007 #3
    In electrical engineering, the maximum power (transfer) theorem states that, to obtain maximum power from a source with a fixed internal resistance, the resistance of the load must be made the same as that of the source.

    when Rs=RL then only maximum power transfer takes place.
    Rs= Source resistance RL = load resistance

    PL = Vin2 /RL = Vin2 / 4RL
     
  5. Dec 6, 2007 #4
    Maxmimum Power Transfer Theorem

    Help me in understanding the cascading of amplifier without loading effect.
     
  6. Dec 7, 2007 #5

    berkeman

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    Actually, that's not quite correct. Think in more general terms, and expand the concept of resistance to a full complex impedance. Then what does the maximum power transfer theorem say?
     
  7. Dec 7, 2007 #6

    berkeman

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    Cascading amplifiers may or may not use matched impedances. Can you tell us a few examples of each -- when would you want the Zin of a stage to match the Zout of the previous stage? When would it be better to have a low Zout compared to a high Zin of the next stage?
     
  8. Dec 9, 2007 #7
    Multistage amplifiers are made up of single transistor amplifiers connected in cascade. The first stage usually provides a high input impedance to minimize loading the source (transducer). The middle stages usually account for most of the desired voltage gain. The final state provides a low output impedance to prevent loss of signal (gain), and to be able to handle the amount of current required by the load. In analyzing multistage amplifiers, the loading effect of the next stage must be considered since the input impedance of the next stage acts as the load for the current stage. Therefore the ac analysis of a multistage amplifier is usually done starting with the final stage. The individual stages are usually coupled by either capacitor or direct coupling.

    http://www.ece.vt.edu/ece3274/twostage.pdf -
     
  9. Dec 9, 2007 #8
  10. Dec 11, 2007 #9
    ----------------------------

    Basically you can forget about loading effects after the 1st year of your engineering course. But in short the internal resistance of the voltmeter (or ammeter) gets added parallel (or series) with resisitance under measurement and hence gives you a slight error in the voltage (or current) reading.

    Max power transfer thm actually has nothing to do here, as you don't want any transfer of power to your multimeter (if this happens you'll waste so much power just making the measurement which will be wrong anyway.)

    Got it?
     
  11. Dec 12, 2007 #10

    berkeman

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    That's a very confusing and misleading post, unplebian. First of all, yes you do need to consider loading effects, basically in every circuit that you design, build or analyze. That's one reason that working EEs use SPICE so much -- to sort through subtle loading and transfer function issues.

    And the original poster (OP) has been asking two separate questions: the loading issue, and the maximum power transfer issue. They are not really the same issue.
     
  12. Dec 12, 2007 #11
    Hi Berkman,

    Thanks for your response. I haven't really seen any place where the loading effect is explicitly dominant. As for spice, there may be no loading effects in spice, but there are also no parasitics there as well.

    Can you please provide some examples where the loading effect will be dominant to cause an error in reading? (Just so that I understand it properly now)

    Thanks.
     
  13. Dec 15, 2007 #12
    In case of csacading of two stage of amplifier max. power should be transfered from one stage to another. now here it is recommended that input impedance of stage must be high while output impedance should be low . now my question is that is there any loading of stages and what abt max. power thransfer th. application in this case??
     
  14. Dec 15, 2007 #13
    hi
    while designing I to V converter with 4mA to 20 mA converted to 0 to 5 V , i used inverting operational amplifier based I to V converter with feedback resistor= 300 ohm. this will give me -1.99V to -5.264V now for getting 0 to 5 V I used another non-inverting operational amplifier adder ckt which will add this output voltage with 1V supply & all resistor R1 & Rf as 1Kohm . if i used other low value resistor then loading will occur & will not get proper result .

    i had tested this on Multisim-8 package
     
  15. Dec 16, 2007 #14
    Most DMMs now-a-days have an input impedance of 10-20MEG ohms. I really doubt if they have huge loading effects. Were you using a classical analog meter? Plus wrt opamps, I think the error was due to your feedback resistor being too low, not beacasuse ofloading error.
     
  16. Dec 16, 2007 #15

    berkeman

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    I didn't mean to suggest that loading effects dominate. They just can't be discountede out of hand. Modeling parasitics is an important part of real-world SPICE work.
     
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