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Interview Q - CMOS inverter

  1. Jul 31, 2011 #1
    Heres an interview question which I am having trouble with:

    Consider a CMOS inverter. Replace the NMOS in it with a PMOS. How would the VTC curve look like?

    I was told that one PMOS would always be in saturation.

    Since the source voltage of the lower PMOS is tied to Vout, how can we figure out if the lower PMOS is cutoff or not.

    Help.
     
  2. jcsd
  3. Jul 31, 2011 #2

    es1

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    So Vs of the new PMOS is Vout and the gates are still wired together, right?

    To draw a VTC you'll need to make some assumptions about the transistors (for example, matched or not matched). Can you think of any others?

    Start drawing the VTC by just picking one point, say Vg=0V. What is Vout for this point? Then work you way up to VDD.

    The follow up question is pretty easy once you have the VTC. Once you have the VTC you can also evaluate the statement, one PMOS is always in saturation (note: saturation means vgs>vt & vds>vgs-vt).
     
  4. Jul 31, 2011 #3
    Yes the Vs of the new PMOS is Vout, and gates are wired together.

    My question was, even if i start with Vg=Vin= 0 and work my way up=> how do you figure out the Vgs of the lower PMOS? since the source of the lower PMOS is set to Vout. How can we figure out if Vgs(lower pmos) is > or < Vt? aka if its cutoff ?

    for the lower pmos, the condition Vsd < Vgs - Vt(p-lower) is always met, however I cannot figure out if Vgs < Vt is met.

    sorry I am very new to cmos.
     
  5. Aug 1, 2011 #4

    es1

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    Finding Vout exactly when Vg=0 is tricky. To do it requires knowledge of the transistors Vt. I'll do this point on the VTC curve for you with the assumption that the transistors are perfectly matched and assume that Vdd>Vt. You should be able to do the other points in the same way.

    Since the top transistor has Vs=Vdd and Vg=0V, Vsg=Vdd>Vt, it is on. Because it is on current can pass from its source to drain.

    If the bottom transistor were off then it would allow no current from source to drain. Current would flow through the upper until Vs=Vd on it. But this would make the lower's Vsg=Vdd>Vt, which would make it on as well. This is a contradiction so the initial assumption was wrong and both the lower and upper are on.

    On the lower, Vg=Vd=0V, Vs=Vout and Vt>0. Thus Vsd=Vsg and Vsd < Vgs - Vt is not met. The lower is therefore on & linear.

    For the upper Vs=Vdd, Vg=0V, Vd=Vout. So Vsg=Vdd and Vsd=Vdd-Vout. Since Vout>Vt (see the argument above) the upper is on & saturated.

    Now its just KCL at Vout. Isd(upper)=Isd(lower).

    Using mathematica:
    Simplify[Solve[ K ((vdd - vt) (vdd - vout) - (vdd - vout)^2/2)==K/2 (vout - vt)^2 ,vout]]

    Which yields:
    [tex]\left\{\left\{\text{vout}\to -\frac{\sqrt{(\text{vdd}-\text{vt})^2}}{\sqrt{2}}+\text{vt}\right\},\left\{\text{vout}\to \frac{\sqrt{(\text{vdd}-\text{vt})^2}}{\sqrt{2}}+\text{vt}\right\}\right\}[/tex]

    And if I use vdd=3.3 and vt=1.7 (from the BSS84) I get vout=2.83V which matches pretty closely to the spice value of 2.86V.
     
    Last edited: Aug 1, 2011
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