J-K Flip Flop wave forms

[bec13]

I understand that the truth table involved, and how it works, but i don't get the timing of the diagrams. I've looked on numerous internet sites and through many books but i still don't understand how when J=K=0 and CLK= up, with Q having no change, that the out put (Q) is up, when the others are down. My confusion continues throughout the entire waveform, mostly i believe, as i do not understand the timings of the CLK.

Is there a set time of CLK between each of the inputs? Basically, i would just like a straight answer to explain to me how the waveform works:)

 

[MATLABdude]

I understand that the truth table involved, and how it works, but i don't get the timing of the diagrams. I've looked on numerous internet sites and through many books but i still don't understand how when J=K=0 and CLK= up, with Q having no change, that the out put (Q) is up, when the others are down. My confusion continues throughout the entire waveform, mostly i believe, as i do not understand the timings of the CLK.

Is there a set time of CLK between each of the inputs? Basically, i would just like a straight answer to explain to me how the waveform works:)

http://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop

Note that transitions in the flip-flop state occur only on the rising clock edge, not when the clock is stable. Additionally, the particular case you ask about, J=K=0 with a rising clock edge (and not a HIGH clock) holds the present state of the flip-flop. J=K=1 with a rising clock edge causes the flip-flop state to toggle. Why? That's the defined function of the J-K flip-flop.

 

[oswaler]

The waveform of a J-K Flip Flop is determined by the inputs of J and K, as well as the clock signal (CLK). The timing of the CLK signal is crucial in understanding the waveform.

When J and K are both 0, the output (Q) remains the same as its previous state, regardless of the CLK signal. This is because the J-K Flip Flop is a type of sequential logic circuit, meaning that the output is dependent on the previous input.

The CLK signal acts as a trigger for the J-K Flip Flop, causing it to change states. When the CLK signal is rising (up), it allows any changes in J and K to affect the output. However, when the CLK signal is falling (down), the outputs are "locked" and cannot be changed. This is why, in the scenario you described, with J and K both 0 and the CLK signal rising, the output remains the same.

The timing of the CLK signal is determined by the specific circuit design and can vary. It is important to note that the timing of the CLK signal is typically faster than the inputs, meaning that the inputs may change multiple times within one CLK cycle. This is why the waveform of a J-K Flip Flop may seem complex and difficult to understand.

In summary, the waveform of a J-K Flip Flop is determined by the inputs of J and K, as well as the timing of the CLK signal. The CLK signal acts as a trigger for the circuit, allowing the outputs to change only when it is rising. The specific timing of the CLK signal can vary and may be faster than the inputs, resulting in a complex waveform. I hope this explanation helps clarify the timing and functionality of the J-K Flip Flop waveform.