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J-K Flip Flop wave forms

  1. Nov 15, 2008 #1
    I understand that the truth table involved, and how it works, but i don't get the timing of the diagrams. Ive looked on numerous internet sites and through many books but i still don't understand how when J=K=0 and CLK= up, with Q having no change, that the out put (Q) is up, when the others are down. My confusion continues throughout the entire waveform, mostly i believe, as i do not understand the timings of the CLK.

    Is there a set time of CLK between each of the inputs? Basically, i would just like a straight answer to explain to me how the waveform works:)
     
  2. jcsd
  3. Nov 16, 2008 #2

    MATLABdude

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    http://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop

    Note that transitions in the flip-flop state occur only on the rising clock edge, not when the clock is stable. Additionally, the particular case you ask about, J=K=0 with a rising clock edge (and not a HIGH clock) holds the present state of the flip-flop. J=K=1 with a rising clock edge causes the flip-flop state to toggle. Why? That's the defined function of the J-K flip-flop.
     
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