J_k flip flop .by using vhdl

  • #1
j_k flip flop .by using vhdl ..plz help

hi every body

i hope every things gana be okay

i really have pro,,in my class

so any one can help me plz give is hand to help

any ways ,, my problem is about ,, my doctor give us hw about some things we don't know how to do , so it's about how can design j
j-k flip flop by using vhdl

anyways ,, tnaks alot
 

Answers and Replies

  • #2
10
0


try this:

Entity T_FF IS
PORT( T, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC;
END T_FF;
ARCHITECTURE Behavior OF T_FF IS
signal tmp : STD_LOGIC;
BEGIN
PROCESS (Clock)
BEGIN
IF Clock' EVENT AND Clock = '1' THEN
if T = '1' THEN
tmp <= NOT tmp;
else
tmp <= tmp;
end IF;
END IF;
END PROCESS;
Q <= tmp;
END Behavior
 
  • #3


thanks a lot for help



and i still search for good one
 

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