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A JFET biased junctions

  1. Aug 3, 2017 #1
    I have a understanding problem with the JFET Transistor. I need this for the exam.
    Gate-Source Voltage = 0V.
    How are the PN Junction biased between Drain and Gate and Gate and Drain.
    For the following cases.
    Vds = 0V this sould be the thermal equilibrium
    Vds < Vdsat (both reverse ?)
    Vds > Vdsat (both reverse ?)

    The exercise is i have to draw the bandstrucutre at source contact and in the pinched off region at the drain contact.
    Last edited by a moderator: Aug 3, 2017
  2. jcsd
  3. Aug 3, 2017 #2


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    you have labelled your post with an "A" tag... post graduate level of education.
    what has your research told you so far ?
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