1. PF Contest - Win "Conquering the Physics GRE" book! Click Here to Enter
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Logic circuit design

  1. May 15, 2017 #1
    1. The problem statement, all variables and given/known data
    The block diagram of FIGURE 3 shows a three-stage asynchrononous counter that is used to count a series of randomly occurring input pulses. The ‘Q’ outputs of the counter are used to drive a logic circuit that gives the output shown in TABLE 1.

    (a) Design the counter using type D flip-flops and simulate your design in PSpice, producing waveforms to confirm the circuit’s operation.

    (b) Design the logic circuit to realise the desired ABCD outputs and simulate your design in PSpice, again producing waveform to demonstrate the circuit’s operation.


    2. Relevant equations

    3. The attempt at a solution

    Hi, could you please help.

    I managed to run simulation regarding a), but looking closer at Table 1 looks like the counter could be reset at Input Pulse 8 as the state of outputs start repeating itself. Would this be correct?

  2. jcsd
  3. May 15, 2017 #2


    User Avatar
    Homework Helper
    Gold Member

    You are correct in your observation. But the counter is not "resetting itself". It is simply going to the next state following state 7 (state 0).
  4. May 15, 2017 #3
    Does it mean that using 10 different output states (0 to 9) as an input to the logic circuit would be a good approach?
  5. May 15, 2017 #4


    User Avatar
    Homework Helper
    Gold Member

    With 3 D-flops, represented by their outputs Q1, Q2, and Q3 you can have only 8 distinct states.
  6. May 15, 2017 #5
    Thanks! Just realised that! 2^3=8 states (0 to 7). Not sure how to decode 3 inputs into 4 outputs designing a logic circuit. Any hints?
  7. May 15, 2017 #6


    User Avatar
    Homework Helper
    Gold Member

    Start by drawing a truth table for your Logic box. From there, you will construct 4 boolean equations, one for output D, one for C, and so on. Those equations can be simplified (if you want to minimize the number of logic gates needed to build) using boolean math or Karnaugh maps. I hope you have already been introduced to this. If not, you might have some self-study to do.
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted

Similar Threads - Logic circuit design Date
Designing a 2-bit Comparator with NOR gates Nov 4, 2017
Need help in designing a logic circuit Feb 1, 2015
Design the logic circuit Jan 22, 2015
Logic circuit design Oct 6, 2013
Logic Design - Combinational Circuits Oct 22, 2010