# Making memory cells

## Main Question or Discussion Point

This is my first post here, be gentle please ^_^. I searched for answers, but nothing came up. This is not homework, it's something I've been working on after I got bored with my Arduino.

I'm working on a small project in my spare time. Using just discrete transistors, I'm building an adding machine. I've got one full adder built using NOR logic and it works great. I'd like to store the output of each adder in a memory cell, but I can't figure out how to make a memory cell. I've seen schematics of 6T sram cells, but I've also read about 1T and 2T sram cells. I don't see how that can be done, but in the pursuit of efficiency and minimizing the number of transistors I use, I'd like to investigate this. Any idea how they make those cells?

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berkeman
Mentor
This is my first post here, be gentle please ^_^. I searched for answers, but nothing came up. This is not homework, it's something I've been working on after I got bored with my Arduino.

I'm working on a small project in my spare time. Using just discrete transistors, I'm building an adding machine. I've got one full adder built using NOR logic and it works great. I'd like to store the output of each adder in a memory cell, but I can't figure out how to make a memory cell. I've seen schematics of 6T sram cells, but I've also read about 1T and 2T sram cells. I don't see how that can be done, but in the pursuit of efficiency and minimizing the number of transistors I use, I'd like to investigate this. Any idea how they make those cells?
Welcome to the PF.

I'm not familiar with 2T ram cells, but I can tell you for sure that 1T "sram" cells need to be refreshed. They are really misnamed dram cells. Do you have any pointers to the 2T ram cells?

Welcome to the PF.

I'm not familiar with 2T ram cells, but I can tell you for sure that 1T "sram" cells need to be refreshed. They are really misnamed dram cells. Do you have any pointers to the 2T ram cells?
Sorry it was 3T and 1T sram cells that I meant, not 2T. I haven't been able to find anything short of descriptions in patent docs. I'm not particularly worried about how many I use, but it would obviously be better to use fewer. To be entirely honest I'm not even sure how the 6T cell works. I've only started messing at this level. I think that arduino has dampened what I thought i knew. I tried copying the diagram for another 6T memory cell hoping that would help me figure out how it works, but it doesn't seem to have. I'm not really sure if I've even copied it right :(. Here's my diagram.

[PLAIN]http://zapdos.ath.cx/sram2.png [Broken]

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berkeman
Mentor
Maybe this will help (it shows FETs instead of BJTs, but the operation is similar):

http://en.wikipedia.org/wiki/Static_RAM

.
I've read through that a bit, but it still doesn't make as much sense as I'd like it to. I'm assuming that mosfets and bjts are similar enough to be used interchangeably for this project. I've still got a ton of bjts left after building all the adders. I'm not really worried about efficiency, I just want it to work. All my transistors are the same though, NPN type ECB. SRAM's seem better suited since they don't need to be refreshed constantly.

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...... I just want it to work. All my transistors are the same though, NPN type ECB........
ECB is the transistor pinout: Emitter, Collector, Base.

Bob S

ECB is the transistor pinout: Emitter, Collector, Base.

Bob S
Yup. I've made an adder with ECB transistors. All the diagrams for sram cells that I've seen call for 6 transistors, 4 NPN and two PNP. I don't have the PNP types, just the NPN. I wonder how to make a memory cell using just NPN transistors.