I was studying this from some info in found online and i couldnt understand something: "Although this circuit (J-K) is an improvement on the clocked SR flip-flop it still suffers from timing problems called "race" if the output Q changes state before the timing pulse of the clock input has time to go "OFF". To avoid this the timing pulse period ( T ) must be kept as short as possible (high frequency). As this is sometimes not possible with modern TTL IC's the much improved Master-Slave JK Flip-flop was developed." Firstly, what is 'race' exactly? why would it even happen? Also, i cant understand how its really functioning and why we give the slave's feedback to the master...i'd be really be glad if someone could explain... thanks.