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Master-Slave flip flop

  1. Nov 30, 2012 #1
    I was studying this from some info in found online and i couldnt understand something:

    "Although this circuit (J-K) is an improvement on the clocked SR flip-flop it still suffers from timing problems called "race" if the output Q changes state before the timing pulse of the clock input has time to go "OFF". To avoid this the timing pulse period ( T ) must be kept as short as possible (high frequency). As this is sometimes not possible with modern TTL IC's the much improved Master-Slave JK Flip-flop was developed."

    Firstly, what is 'race' exactly? why would it even happen?
    Also, i cant understand how its really functioning and why we give the slave's feedback to the master...i'd be really be glad if someone could explain...

  2. jcsd
  3. Dec 1, 2012 #2
    The first register of the master slave flip-flop captures its input on a clock edge. Its output is subsequently transferred to a second register which captures on the opposite edge of the clock. This prevents the second flip flop from trying to capture data from the first while the first register's output is in transition.

    This was a common technique many (20+) years ago but is not how we manage digital logic timing these days except in very special circumstances.

    You may be reading from something very old.
  4. Dec 1, 2012 #3
    really? so master-slave jks arent used much nowadays?
  5. Dec 1, 2012 #4
    Master slave JK flipflop was a device and concept that dates back to the MSI era.
    We are currently in the VLSI era.
  6. Dec 1, 2012 #5
    thanks for enlightening me...
  7. Dec 2, 2012 #6
    Maybe it was not an explanation, but at least it was excellent advice.

    JK were used three decades ago with TTL circuitry. Nearly since CMOS took over, only D latches and D flip-flop exist. Race-safe behaviour is very complicated to understand and design, needs other circuits than a master-slave to accept any delay condition, and is radically different with CMOS circuitry.

    There is more than enough to learn and understand in circuitry, you can happily drop what is abandoned.
  8. Dec 2, 2012 #7
    I learned about master-slave flip-flops as a student many years ago. The idea was to prevent the downstream flip-flop from firing early due to clock skew by delaying its actions by half clock period. At the time I remember thinking it was a clever technique. However, it turns out that you are paying a very high price for sweeping clock skew under the rug in this brute force way.

    Consider two flip-flops that could potentially transfer data at 100MHz: sending flipflop has 5ns clock to out, receiving flip-flop requires 5ns setup time, and assume no clock skew:
    10ns required from rising edge to rising edge = 100MHz.

    Operating these in a master-slave fashion would limit rate to 50MHz, 10ns required from rising edge to falling edge of clock.

    Giving up a full 50% in speed in order to ignore clock skew was not an idea that lasted very long, increased clock speed has been a primary goal in the evolution of digital logic.
    Last edited: Dec 2, 2012
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