Max Current in CMOS Inverter with Given Parameters

In summary: Vout. If the input is 0, so is Vgs, so is Vout.So think of Vg as the input voltage, Vin. The input voltage is either 0 and Vout is high, or VDD and Vout is low. That's the definition of an inverter. So if you're asked for the current into the output (from the previous stage, we assume), it's the current through the P device, and that is IP = k'p(W/L)p(VDD-Vg-Vtp)^2.I'm sure you can figure out the rest. In summary, the question asks for the maximum current that a digital logic inverter can sink or source
  • #1
perplexabot
Gold Member
329
5
Hi all, I have gave this question a lot of thought but can't seem to get anywhere. Any help will be much appreciated.

Homework Statement


For a digital logic inverter for which k'n = 120 uA/V^2, k'p = 60 uA/V^2, Vtn = |Vtp| = .7V, VDD = 3V, Ln = Lp = .8 um, Wn = 1.2 um and Wp = 2.4 um, find:

the maximum current that the inverter can sink or source while the output remains within .1V of ground or VDD respectively.


Homework Equations


(attached as an image)


The Attempt at a Solution


No idea what to do. I can't even start to think about this one. I know that when Vout = Vdd/2, max current is achieved since (if Vdd is large enough) both mosfets are in saturation. Is that right? But I don't think this has anything to do with this question, since we are restriced to .1V from ground or VDD. I do not understand what is meant by the solution manual, please HELP.

I have also attached the answer in the solution manual, it makes no sense to me. Please help me out. This question is bothering me. Thank you
 

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  • #2
Attachments?

Anyway, you're right about this not being a linear mode of operation.
 
  • #3
rude man said:
Attachments?

Anyway, you're right about this not being a linear mode of operation.

Oops. Forgot about the attachment. I have edited my post with the attachment. Thank you.
 
  • #4
EDIT

never mind, I see it's supposed to be a CMOS output stage.
 
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  • #5
rude man said:
The problem is I don't know what the equations for modeling a MOS transistor you were given. Those symbols are not standard. You need to give us your model using those symbols, or at least write their definitions out in full.

In other words,
Ids = Ids(k,Vtn,L,W,Vgate-Vsource, Vdrain-Vsource, etc. ).

Also: is this a CMOS output or just an NMOS? If CMOS there are two answers to this question, one when the output is close to Vdd and one when it's close to ground. (NMOS and PMOS have different models).

Hey, thanks for your help. I have attached an image of the Id - Vgs relations that we use. I have also included two equations that greatly resemble the solution manual. Let me know what you think.
 
  • #6
Good , but where are the image and equations?
 
  • #7
rude man said:
Good , but where are the image and equations?

In my original post (first post). I now have two attachments. I should have mentioned that, sorry.
 
  • #8
I still don't see a circuit diagram, but I'm going to assume the circuit applies VDD to the gate of the N channel device:

OK, so from what I gleaned from that,
for the N channel device,

Ids = k(W/L){(Vgs - VT)Vds - (1/2)Vds2}
where
Vgs = voltage from source to gate
Vds = voltage from source to drain.
Both voltages are > 0.

So now use that equation to solve for Ids which is the output current (sinking current) of your circuit when the output voltage is to be +0.1V. Hint: (1/2Vds2 << (Vgs - VT)Vds).

Then do the same for the P channel device using the p constants given you. Except now the output voltage is to be VDD - 0.1V. Watch your polarities for the P device!


BTW the equation for "I_peak" in your 1st image is totally irrelevant.
 
  • #9
rude man said:
I still don't see a circuit diagram, but I'm going to assume the circuit applies VDD to the gate of the N channel device:

OK, so from what I gleaned from that,
for the N channel device,

Ids = k(W/L){(Vgs - VT)Vds - (1/2)Vds2}
where
Vgs = voltage from source to gate
Vds = voltage from source to drain.
Both voltages are > 0.

So now use that equation to solve for Ids which is the output current (sinking current) of your circuit when the output voltage is to be +0.1V. Hint: (1/2Vds2 << (Vgs - VT)Vds).

Then do the same for the P channel device using the p constants given you. Except now the output voltage is to be VDD - 0.1V. Watch your polarities for the P device!


BTW the equation for "I_peak" in your 1st image is totally irrelevant.

Thanks for your reply. I have 2 questions though. Before I ask my questions, I need to clarify that VDD is NOT applied to the NMOS gate. I have finally attached a schematic for reference.

First, how do u know that the NMOS is in triode mode?
Second, how do I know what Vin (AKA Vg for NMOS AKA Vg for PMOS) is for a given Vout. For example, how can I get Vg for the NMOS knowing that the output is .1V from ground? I know it will be around VDD since this is a CMOS inverter, but how can I get a precise answer?
 

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  • #10
perplexabot said:
Thanks for your reply. I have 2 questions though. Before I ask my questions, I need to clarify that VDD is NOT applied to the NMOS gate. I have finally attached a schematic for reference.
Oh, but I think it is. I'm talking about what's labeled vl on your schematic diagram. That input comes from a similar circuit's output and will be very close to VDD when the previous stage output is high,

The reason I'm confident is that that way we get the right answer!


First, how do u know that the NMOS is in triode mode?
Because I picked the equation for the case where Vds < (Vgs - VT). You understand that? Why they call it 'triode' mode I have no idea. Probably dumb. A triode is a vacuum tube!

Second, how do I know what Vin (AKA Vg for NMOS AKA Vg for PMOS) is for a given Vout. For example, how can I get Vg for the NMOS knowing that the output is .1V from ground? I know it will be around VDD since this is a CMOS inverter, but how can I get a precise answer?

It's an inverter. The N device turns on and the P device turns off. So that means that if the input is +VDD, so is Vgs for the N device and the output tries to go to 0V. The reason the output goes only to 0.1V in your case is that there is a source of current like a load resistor tied to the output going to VDD that is sourcing current into the drain. Without a source of current the output will be very close to VDD. That current is what you're computing as your answer.

Similarly, when the input is close to 0V, the output tries to swing to +VDD via the P channel device turning on. For this device, Vsg = VDD also. The output won't quite make it to VDD, again if there is a current sink tied to the output, for example a load resistor going to ground. It's exactly analogous to the N channel device.

Try to get comfortable with the polarities involved with N vs. P channel devices:
N channel: gate voltage > source voltage to turn on. Vd > Vs. Vs is typically at ground.
P channel: gate voltage < source voltage to turn on. Vs > Vd. Vs is typically at VDD.

 

1. What is the maximum current that can flow through a CMOS device?

The maximum current that can flow through a CMOS device is determined by the size of the transistors used in the device. Generally, the larger the transistor, the higher the maximum current that can flow through it. However, the maximum current is also limited by the device's power supply and the thermal limitations of the materials used.

2. How does the maximum current affect the performance of a CMOS device?

The maximum current through a CMOS device affects its performance in several ways. First, a higher maximum current allows the device to switch faster, resulting in faster operation. Additionally, a higher maximum current can improve the noise margin, making the device more resistant to signal interference. However, a higher maximum current can also increase power consumption and heat generation, potentially reducing the device's lifespan.

3. How can the maximum current through a CMOS device be controlled?

The maximum current through a CMOS device can be controlled by adjusting the size and layout of the transistors used in the device. By changing the dimensions of the transistors, the maximum current can be increased or decreased. Additionally, external circuitry, such as current-limiting resistors, can be used to further control the maximum current through the device.

4. What are the consequences of exceeding the maximum current through a CMOS device?

If the maximum current through a CMOS device is exceeded, it can lead to overheating and potentially damaging the device. In extreme cases, it can even cause the device to fail completely. It is important to carefully design and control the maximum current through a CMOS device to ensure its proper functioning and longevity.

5. Can the maximum current through a CMOS device be increased beyond its specified limit?

In most cases, the maximum current through a CMOS device cannot be increased beyond its specified limit without risking damage to the device. However, some techniques such as parallelization, where multiple devices are used in parallel, can effectively increase the maximum current. It is important to carefully consider the limitations and design of a CMOS device before attempting to increase the maximum current.

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