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Max current through CMOS

  1. Feb 18, 2013 #1

    perplexabot

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    Hi all, I have gave this question a lot of thought but can't seem to get anywhere. Any help will be much appreciated.

    1. The problem statement, all variables and given/known data
    For a digital logic inverter for which k'n = 120 uA/V^2, k'p = 60 uA/V^2, Vtn = |Vtp| = .7V, VDD = 3V, Ln = Lp = .8 um, Wn = 1.2 um and Wp = 2.4 um, find:

    the maximum current that the inverter can sink or source while the output remains within .1V of ground or VDD respectively.


    2. Relevant equations
    (attached as an image)


    3. The attempt at a solution
    No idea what to do. I can't even start to think about this one. I know that when Vout = Vdd/2, max current is achieved since (if Vdd is large enough) both mosfets are in saturation. Is that right? But I don't think this has anything to do with this question, since we are restriced to .1V from ground or VDD. I do not understand what is meant by the solution manual, please HELP.

    I have also attached the answer in the solution manual, it makes no sense to me. Please help me out. This question is bothering me. Thank you
     

    Attached Files:

    Last edited: Feb 18, 2013
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  3. Feb 18, 2013 #2

    rude man

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    Attachments?

    Anyway, you're right about this not being a linear mode of operation.
     
  4. Feb 18, 2013 #3

    perplexabot

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    Oops. Forgot about the attachment. I have edited my post with the attachment. Thank you.
     
  5. Feb 18, 2013 #4

    rude man

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    EDIT

    never mind, I see it's supposed to be a CMOS output stage.
     
    Last edited: Feb 18, 2013
  6. Feb 18, 2013 #5

    perplexabot

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    Hey, thanks for your help. I have attached an image of the Id - Vgs relations that we use. I have also included two equations that greatly resemble the solution manual. Let me know what you think.
     
  7. Feb 18, 2013 #6

    rude man

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    Good , but where are the image and equations?
     
  8. Feb 18, 2013 #7

    perplexabot

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    In my original post (first post). I now have two attachments. I should have mentioned that, sorry.
     
  9. Feb 18, 2013 #8

    rude man

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    I still don't see a circuit diagram, but I'm going to assume the circuit applies VDD to the gate of the N channel device:

    OK, so from what I gleaned from that,
    for the N channel device,

    Ids = k(W/L){(Vgs - VT)Vds - (1/2)Vds2}
    where
    Vgs = voltage from source to gate
    Vds = voltage from source to drain.
    Both voltages are > 0.

    So now use that equation to solve for Ids which is the output current (sinking current) of your circuit when the output voltage is to be +0.1V. Hint: (1/2Vds2 << (Vgs - VT)Vds).

    Then do the same for the P channel device using the p constants given you. Except now the output voltage is to be VDD - 0.1V. Watch your polarities for the P device!


    BTW the equation for "I_peak" in your 1st image is totally irrelevant.
     
  10. Feb 18, 2013 #9

    perplexabot

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    Thanks for your reply. I have 2 questions though. Before I ask my questions, I need to clarify that VDD is NOT applied to the NMOS gate. I have finally attached a schematic for reference.

    First, how do u know that the NMOS is in triode mode?
    Second, how do I know what Vin (AKA Vg for NMOS AKA Vg for PMOS) is for a given Vout. For example, how can I get Vg for the NMOS knowing that the output is .1V from ground? I know it will be around VDD since this is a CMOS inverter, but how can I get a precise answer?
     

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  11. Feb 18, 2013 #10

    rude man

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    It's an inverter. The N device turns on and the P device turns off. So that means that if the input is +VDD, so is Vgs for the N device and the output tries to go to 0V. The reason the output goes only to 0.1V in your case is that there is a source of current like a load resistor tied to the output going to VDD that is sourcing current into the drain. Without a source of current the output will be very close to VDD. That current is what you're computing as your answer.

    Similarly, when the input is close to 0V, the output tries to swing to +VDD via the P channel device turning on. For this device, Vsg = VDD also. The output won't quite make it to VDD, again if there is a current sink tied to the output, for example a load resistor going to ground. It's exactly analogous to the N channel device.

    Try to get comfortable with the polarities involved with N vs. P channel devices:
    N channel: gate voltage > source voltage to turn on. Vd > Vs. Vs is typically at ground.
    P channel: gate voltage < source voltage to turn on. Vs > Vd. Vs is typically at VDD.

     
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