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Memory Bus Addressing

  1. Sep 27, 2007 #1
    I've been looking at system architectures, and it seems almost always, a specific device on the memory bus uses a staggered type of addressing. What I mean by this is that say you have a chip select exclusive to 1 device. The address bus may have lines A[25:0], but instead of matching each address up (A0 of the memory controller to A0 of the device, A1 to A1, and so on), they are offset like maybe A10-A22 of the controller are attached to A0-A12 of the peripheral correspondingly.

    I know each chip select has its own mapping, but why bother with the different addressing offsets? If its important, how do I know what I'm doing? There seems little reason that I can see from just looking at a schematic. I know some devices have page mode, where you're actually accessing a chunk of data, so maybe this is the only reason to have offsets? Along these lines, I've noticed almost always that the LSB of the controller address lines are the ones skipped.

    Please, can someone with some experience with this give me an idea of what's going on here? Any tips for when I want to do this with different devices?
     
  2. jcsd
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