Moore circuit timing diagram

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Homework Statement



Fig. 3-3 is a Moore type sequential circuit composed of a positive edge triggered D flip-flop and a combinational circuit. X is input, Y is an output, and CLK is a clock. Please show how Qo, Q1, and Y change when input X is given to this circuit at the timing diagram shown in Figure 3-4.


I got the answer is y=0 but in timing diagram it is not zero why?

wrMIW.jpg

kLCGm.jpg

my attempt to draw timing diagram
vAz2s.jpg



Why y is not zero in timing diagram?

Figure 3-5 shows the state transition diagram of Moore type sequential circuit M that observes the time series of input X and outputs 1 when time series 010 or 101 appears, and 0 otherwise (Incomplete). Let S0 be the initial state (assume that 0 is input consecutively twice or more consecutively) and complete this state transition diagram according to the notation without increasing the number of states. Note that the time series will continue indefinitely.

DsY2X.jpg


Here i really dont understand what the question want?
Should i make 010/101 from the diagram?
Can someone give me hint?
Thankyou!!!!!




The Attempt at a Solution

 

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Answers and Replies

  • #2
lewando
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Why y is not zero in timing diagram?
Why do you think it should be? What are the levels of the inputs to the AND gate during the 5th clock cycle?
 
  • #3
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Why do you think it should be? What are the levels of the inputs to the AND gate during the 5th clock cycle?
it is q1=x and ##\bar{q_0}##=##\bar{x}##. then ##y=\bar{x}.x=0## right?
what do you mean level input?
in the 5th clock cycle y produces 1?
 
  • #4
lewando
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it is q1=x and ¯^q0q0^¯\bar{\hat{q_0}}=¯^x
Don't punish yourself (and others) with unnecessary notation. Use /Q0 or ~Q0 or Q0' to indicate the "Q-not" signal.

what do you mean level input?
I mean logic level. Either a 1 or 0.

in the 5th clock cycle it produces 1?
Your attempt to draw the timing diagram shows Y being a "1" and a "0" at the same time, for the 5th clock cycle. If you are saying that it should be a "0", you are incorrect. I ask again: what are the logic levels at the inputs of the AND gate for the 5th clock cycle?
 
  • #5
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Don't punish yourself (and others) with unnecessary notation. Use /Q0 or ~Q0 or Q0' to indicate the "Q-not" signal.


I mean logic level. Either a 1 or 0.


Your attempt to draw the timing diagram shows Y being a "1" and a "0" at the same time, for the 5th clock cycle. If you are saying that it should be a "0", you are incorrect. I ask again: what are the logic levels at the inputs of the AND gate for the 5th clock cycle?
it is 1?
as you can see in my picture, ~Q0 =1 and q1=1 right?
 
  • #6
lewando
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~Q0 =1 and q1=1 right?
In clock cycle 5, you are correct. So based on that, for clock cycle 5, what logic level do you think Y should be?

By the way, be consistent in your notation. Rather than "~Q0 =1 and q1=1", which mixes boldface and capitalization, better "~Q0 =1 and Q0=1" or "~Q0 =1 and Q1=1". Whatever you prefer.
 
  • #7
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In clock cycle 5, you are correct. So based on that, for clock cycle 5, what logic level do you think Y should be?

By the way, be consistent in your notation. Rather than "~Q0 =1 and q1=1", which mixes boldface and capitalization, better "~Q0 =1 and Q0=1" or "~Q0 =1 and Q1=1". Whatever you prefer.
y is 1 ,but why when i count ##\bar{q_0}##=##\bar{x}##. then ##y=\bar{x}.x=0## it produce y always zero?
 
  • #8
lewando
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Sorry, I am having trouble understanding what you are asking. I say I'm "sorry" because I try to adhere to the Farsi expression: "the listener has the obligation to understand what the speaker is saying". Or something like that. In this case, I am failing. Can you explain what you are asking another way? Or maybe graphically?
 
  • #9
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Sorry, I am having trouble understanding what you are asking. I say I'm "sorry" because I try to adhere to the Farsi expression: "the listener has the obligation to understand what the speaker is saying". Or something like that. In this case, I am failing. Can you explain what you are asking another way? Or maybe graphically?
y is 1 in 5th clock cycle
when i count ##\bar{q_0}##=##\bar{x}##. then ##y=\bar{x}.x=0## it produce ##y=0##, it means y is always zero, why is it different from the one i got in timing diagram? the timing diagram produce all y=0 except in 5th cycle. i want to know why is that happen
 
  • #10
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y is 1 in 5th clock cycle
when i count ##\bar{q_0}##=##\bar{x}##. then ##y=\bar{x}.x=0## it produce ##y=0##, it means y is always zero, why is it different from the one i got in timing diagram? the timing diagram produce y=1 in 5th clock cycle, it should be all y always zero isnt it?
i want to know why is that happen
 
  • #11
lewando
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If what you are saying is that the Q1 input to the AND gate is based on X and the /Q0 input to the AND gate is based on /X, and therefore X AND /X must be 0, then your error is in treating this as a combinational logic circuit. It is not. The sequential (clocked) nature of the circuit must always be considered.
 
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  • #12
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If what you are saying is that the Q1 input to the AND gate is based on X and the /Q0 input to the AND gate is based on /X, and therefore X AND /X must be 0, then your error is in treating this as a combinational logic circuit. It is not. The sequential (clocked) nature of the circuit must always be considered.
ok so you mean, there is no relation between the timing diagram and the output?
 
  • #13
lewando
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No I am not saying that. The timing diagram is closely related (edit: exactly related) to the sequential circuit (which usually has an output). For a given sequential circuit, the timing diagram is used to determine the output. Sometimes you will be given a timing diagram and expected to generate a sequential circuit.
 
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  • #14
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No I am not saying that. The timing diagram is closely related to the sequential circuit (which usually has an output). For a given sequential circuit, the timing diagram is used to determine the output. Sometimes you will be given a timing diagram and expected to generate a sequential circuit.
but why ##y## logic level in 5th clock cycle is 1? while it should be all 0?
is the timing diagram that i drew correct?
 
  • #15
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Hi. Been trying to follow this offline. Not sure that I do :-), but I'll jump in. The OP seems to keep trying to relate the output y to x'. If I'm understanding this correctly, I think lewando's key point...

The sequential (clocked) nature of the circuit must always be considered.
... is that the output is based on a sequential process that precedes it. So the focus would be on what inputs are present at the final AND gate for the clock iteration you're trying to assess.
 
  • #16
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... follow up to above, so this isn't true:

x=0 it produce y=0 it means y is always zero
 
  • #17
lewando
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why y logic level in 5th clock cycle is 1?
You already agreed that this was the case (in posts 5, 7 and 9). In the 5th clock cycle, both inputs to the AND gate are at logic level 1. So why is this not clear?
 
  • #18
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You already agreed that this was the case (in posts 5, 7 and 9). In the 5th clock cycle, both inputs to the AND gate are at logic level 1. So why is this not clear?
i didnt understand what is the different between timing diagram and the result when i count it using boolean algebra?
you said it is closely related but both of them can have different result?
 
  • #19
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Hi. Been trying to follow this offline. Not sure that I do :-), but I'll jump in. The OP seems to keep trying to relate the output y to x'. If I'm understanding this correctly, I think lewando's key point...



... is that the output is based on a sequential process that precedes it. So the focus would be on what inputs are present at the final AND gate for the clock iteration you're trying to assess.
thanks but what you mean by the final AND gate for clock iteration?
 
  • #20
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thanks but what you mean by the final AND gate for clock iteration?
let me re-write that:
The focus is on what input values are at the AND gate--for the clock pulse you care about. That is, the gate that directly outputs y. I was just trying emphasize lewando's point another way. The value of the output y can change with each clock pulse, right? So what determines that output value? The only thing that matters at that moment are the 2 inputs to the AND gate that feeds y.

I think you seem to be getting stuck on the instantaneous value of x or x'. But what I'm trying to say is, that really doesn't matter, because the circuit processes things sequentially. That's like when you're eating breakfast, trying to worry about what you are going to have for lunch. [Or maybe a better way of saying it: suppose you get packages every hour. At 8:00 you deal with the package you get at 8:00. There's another one on the way that will arrive at 9:00, but you can't do anything with it, because you don't know what it is yet.]

Until it's been clocked through, the present value of x is not relevant to the output.
 
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  • #21
lewando
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i didnt understand what is the different between timing diagram and the result when i count it using boolean algebra?
you said it is closely related but both of them can have different result?
The difference is that the timing diagram represents the reality of the circuit whereas the phrase "count it using Boolean algebra", whatever that means, does not represent the reality of the circuit. Let it go...
 
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  • #22
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The difference is that the timing diagram represents the reality of the circuit whereas the phrase "count it using Boolean algebra", whatever that means, does not represent the reality of the circuit. Let it go...
ok thanks! how about second question? i dont understand what it ask, can you give me hint?
 
  • #23
lewando
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It is like a puzzle. As you have stated, it is an incomplete state transition diagram. You need to complete it in such a way that it performs the task of "observes the time series of input X and outputs 1 when time series 010 or 101 appears, and 0 otherwise". The highlighted areas below need your attention.
upload_2018-5-28_2-46-9.png
 

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  • #24
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It is like a puzzle. As you have stated, it is an incomplete state transition diagram. You need to complete it in such a way that it performs the task of "observes the time series of input X and outputs 1 when time series 010 or 101 appears, and 0 otherwise". The highlighted areas below need your attention.
View attachment 226281
i dont understand, is it always start from S0?
0b9UA.jpg


do i need to pay attention to input x only?
is it always start from S0? i know x is input and S is flipflop and S0/.. is output.
such as S0->S1->S2 = 0->1->0 , so output S2/1 ?
then from S2 , i need to go to S3?
 

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  • #25
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It is like a puzzle. As you have stated, it is an incomplete state transition diagram. You need to complete it in such a way that it performs the task of "observes the time series of input X and outputs 1 when time series 010 or 101 appears, and 0 otherwise". The highlighted areas below need your attention.
View attachment 226281
srJNS.jpg

after some youtube tutorial,is it correct?
 

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