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MOSFET circuit problem

  1. May 23, 2014 #1


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    Here is my circuit:


    Q1 is NMOS and Q2 is PMOS.
    Q1: VT1=0.7V, beta1=2mA/V^2
    Q2: VT2=-0.9V, beta2=1.8mA/V^2.
    I assumed that both transistors work in saturation. In this mode it must be:
    Q1: VG1S1 > VT1, VG1D1 < VT1, ID1=beta1*(VG1S1-VT1)^2/2,
    Q2: VS2G2 > -VT2, VD2G2 < -VT2, ID2=beta2*(VS2G2+VT2)^2/2.

    We see on scheme that ID2=IB2. Using KCL we get ID1=IB1-ID2=100uA.
    Using KVL we get VG1S1=VG. If we put VG1S1=VG in our equation for drain's current in saturation mode we get that ID1=9*10^(-5) A so our equation doesn't hold? (ID1=IB1-ID2=100uA.) :confused:
    Last edited: May 23, 2014
  2. jcsd
  3. May 23, 2014 #2


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    I am confused.
    Q1 is a voltage follower that sets the voltage to the common source and 200uA current source.
    Q2 can only have 100uA current sink.
    Q1 current must carry the difference which is –100 uA, (backwards).
    But Q2 is controlled by VB between the drain and gate, not the source.

    You have specified voltages and currents and the V~I relationships.
    There is no degree of freedom, so you have an over-specified contradiction.

    Can you produce a circuit diagram that shows the circuit you are modelling, as it would be implemented between supply rails. That should identify the contradiction.
  4. May 24, 2014 #3


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    This is example from my textbook. Here is complete text and original scheme:
    Find modes of operation of MOSFETs, their Q points, output DC voltage and voltage gain Av. VG=1V, Vt1=0.7V, Vt2=-0.9V, VA1=VA2=20V, beta1=2mA/V^2, beta2=1.8mA/V^2, IB1=200uA, IB2=100uA, VB=1V.

    You can see solution below "Rezultat".

    Attached Files:

    Last edited: May 24, 2014
  5. May 24, 2014 #4


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    MOSFET circuit contradiction

    Just to mention that NI Multisim 13.0 refuses to simulate original circuit, but if I put VG=1.0162V (100*10^-6 approximately equals 2*10^(-3)*(1.0162-0.7)^2/2 so relation ID1=beta1*(VG1S1-VT1)^2/2 is satisfied) instead of Vg=1V Multisim simulates circuit.
    Last edited: May 24, 2014
  6. May 30, 2014 #5


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    Since there are finite Early voltages (VA1=VA2=20V) I must include these voltages in drain's currents like this:
    where lambda is coefficient of channel modulation, lambda=1/VA.
  7. May 30, 2014 #6
    You show as a "folded cascode" amplifier (CS + CG).
    First what you need is to use this equation
    Id1 = 0.5*β*(Vgs1 + Vt1)^2 * (1 + λ*Vds1) and solve is for Vds1.
    Because from inspection we know that Vgs1 = 1V and Id1 = 100μA.
    After we solve this we get Vds1 = 2.22222V. Thanks to this we can find Vgs2 and solve for Vsd2.
    Vgs2 = - 1.22222V and Vsd2 = 1.40309V

    And Vout = Vds1 - Vsd2 = 2.22222V - 1.40309V = 0.81913V

    And simulation (LTspice) shows similar result.

    Edit... And your multisim digram is completely wrong. Q1 is upside down and you have no VDD source.

    Attached Files:

    • ff.PNG
      File size:
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    Last edited: May 30, 2014
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